Integrated Assemblies Having Transistor Body Regions Coupled to Carrier-Sink-Structures; and Methods of Forming Integrated Assemblies

Patent metadata

Field	Value
Publication number	US-2024172432-A1
Application number	US-202418428325-A
Country	US
Kind code	A1
Filing date	Jan 31, 2024
Priority date	Mar 6, 2019
Publication date	May 23, 2024
Grant date	—

Abstract

Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

First claim

I/We claim:

1 . A method of forming an integrated assembly, comprising:
forming a stack comprising, in ascending order, a first semiconductor material, an insulative material, a digit line material, and a second semiconductor material; the first semiconductor material being either p-type doped or n-type doped, and the second semiconductor material being the other of p-type doped and n-type doped; patterning the insulative material, the digit line material, and the second semiconductor material into rails extending along a first direction; the rails being spaced from one another by gaps; regions of the first semiconductor material being exposed along bottom peripheries of the gaps; the rails having sidewalls along the gaps; the patterned digit line material within the rails being digit lines; forming first insulative spacers along the sidewalls of the rails; forming semiconductor extensions along the first insulative spacers; the semiconductor extensions and the first insulative spacers narrowing the gaps; forming second insulative spacers within the narrowed gaps; forming a planarized surface extending across the rails, the first insulative spacers, the semiconductor extensions and the second insulative spacers; forming third semiconductor material over and directly against the planarized surface; forming slits extending through the third semiconductor material to the second insulative spacers; the slits extending linearly along the first direction; forming insulative panels within the slits; forming trenches extending through the third semiconductor material and the insulative panels; the trenches extending along a second direction which crosses the first direction; the trenches patterning the third semiconductor material into pillars comprising transistor body regions; the second semiconductor material comprising first source/drain regions under the transistor body regions; forming gate dielectric material along sidewalls of the transistor body regions; forming wordlines along the gate dielectric material; the wordlines extending along the second direction; forming second source/drain regions within upper regions of the pillars; forming storage elements coupled with the second source/drain regions; wherein the first source/drain regions, the second source/drain regions and the transistor body regions are together incorporated into access transistors; wherein the access transistors and the storage elements are incorporated into memory cells of a memory array; and wherein the extensions are configured to drain excess carriers from the transistor body regions to the first semiconductor material during operation of the memory cells.

2 . The method of claim 1 wherein the storage elements are capacitors.

3 . The method of claim 1 wherein the gate dielectric material consists of silicon dioxide.

4 . The method of claim 1 wherein the insulative material, the first insulative spacers, the second insulative spacers and the insulative panels are all a same composition as one another.

5 . The method of claim 4 wherein the insulative material, the first insulative spacers, the second insulative spacers and the insulative panels all comprise silicon dioxide.

6 . The method of claim 1 wherein at least one of the insulative material, the first insulative spacers, the second insulative spacers and the insulative panels is a different composition relative to another of the insulative material, the first insulative spacers, the second insulative spacers and the insulative panels.

7 . The method of claim 1 wherein the first, second and third semiconductor materials are a same composition as one another.

8 . The method of claim 7 wherein the first, second and third semiconductor materials comprise silicon.

9 . The method of claim 1 wherein at least one of the first, second and third is a different composition from at least one other of the first, second and third semiconductor materials.

Assignees

• Micron Technology Inc

Inventors

• Karda Kamal M
• Liu Haitao
• Ramaswamy Durai Vishak Nirmal
• Gao Yunfei
• Tang Sanh D
• Pandey Deepak Chandra

Classifications

• H10D30/63

  Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) · CPC title

• H10D30/025 Primary

  of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318) · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C5/025

  Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10) · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title