Semiconductor device

Patent metadata

Field	Value
Publication number	US-2024172426-A1
Application number	US-202318346942-A
Country	US
Kind code	A1
Filing date	Jul 5, 2023
Priority date	Nov 22, 2022
Publication date	May 23, 2024
Grant date	—

Abstract

A semiconductor device may include a device isolation layer on a substrate and defining an active region; and a word line structure in a gate trench defined by the device isolation layer and the active region. The word line structure may include a word line on a gate dielectric layer. The word line may include a second material layer including a doped semiconductor material on a first material layer, may have a first region having a first width and a second region having a second width, which may be wider than the first width. The second material layer may include a first material portion in the first region and a second material portion in the second region. The doped semiconductor material may be a first concentration in the first material portion and a second concentration in the second material portion, which may be lower than the first concentration.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate including an active region; a device isolation layer on the substrate and defining the active region; and a word line structure crossing the active region and the device isolation layer, the word line structure being in a gate trench extending in a first horizontal direction, wherein the gate trench is defined by the device isolation layer and the active region, the word line structure includes a gate dielectric layer and a word line, the gate dielectric layer is on an inner wall of the gate trench, the word line is on the gate dielectric layer and partially fills the gate trench, the word line includes a first material layer and a second material layer on the first material layer, the second material layer includes a doped semiconductor material, the word line has a first region having a first width and a second region having a second width, the second width is wider than the first width, the second material layer includes a first material portion in the first region and a second material portion in the second region, the doped semiconductor material of the second material layer has a first impurity concentration in the first material portion and a second impurity concentration in the second material portion, and the second impurity concentration is lower than the first impurity concentration.

2 . The semiconductor device of claim 1 , wherein the doped semiconductor material is polycrystalline silicon containing phosphorus (P) or arsenic (As).

3 . The semiconductor device of claim 1 , wherein the first impurity concentration and the second impurity concentration range from 1.0×10 18 /cm 3 to 1.0×10 22 /cm 3 .

4 . The semiconductor device of claim 1 , wherein an etching rate of a material of the first material portion is a faster than an etching rate of a material of the second material portion.

5 . The semiconductor device of claim 1 , wherein
the word line has a third region having a third width, the third width is wider than the first width and narrower than the second width, the second material layer includes a third material portion in the third region, the doped semiconductor material of the second material layer has a third impurity concentration in the third material portion, and the third impurity concentration is lower than the first impurity concentration and higher than the second impurity concentration.

6 . The semiconductor device of claim 1 , wherein
the gate trench includes a first trench portion extending with a first width and a second trench portion extending with a second width, the second width is wider than the first width, the first region of the word line is in the first trench portion, and the second region of the word line is in the second trench portion.

7 . The semiconductor device of claim 6 , wherein
the device isolation layer is recessed in the first trench portion, and active region is recessed in the second trench portion.

8 . The semiconductor device of claim 6 , wherein
the first material portion is adjacent to the device isolation layer, and the second material portion is adjacent to the active region.

9 . The semiconductor device of claim 6 , wherein
the first trench portion and the second trench portion are provided as a plurality of first trench portions and a plurality of second trench portions, respectively, and the plurality of first trench portions and the plurality of second trench portions are alternately arranged along the gate trench.

10 . The semiconductor device of claim 1 , wherein
the active region and the device isolation layer are recessed by the gate trench, and the gate dielectric layer includes a first portion contacting the device isolation layer and a second portion contacting the active region, and a thickness of the first portion is different from a thickness of the second portion.

11 . The semiconductor device of claim 10 , wherein the thickness of the first portion is thinner than the thickness of the second portion.

12 . The semiconductor device of claim 1 , wherein a thickness of the second material layer in the first region is different from a thickness of the second material layer in the second region.

13 . The semiconductor device of claim 1 , wherein a thickness of the first material layer is thicker than a thickness of the second material layer.

14 . A semiconductor device comprising:
a substrate including an active region, the active region including a first impurity region and a second impurity region; a device isolation layer on a side surface of the active region, the device isolation layer and the active region defining gate trenches crossing the active region and the device isolation layer, the gate trenches extending in a first horizontal direction; word line structures including word lines in the gate trenches; a bit line structure crossing the word lines and electrically connected to the first impurity region, a height level of the bit line structure being different from height levels of the word lines; a storage node contact electrically connected to the second impurity region; and an information storage structure electrically connected to the storage node contact, wherein the gate trenches include a first gate trench and a second gate trench, the word lines include a first word line in the first gate trench and a second word line in the second gate trench, the first word line includes a first doped material having a first impurity concentration in a region having a first width, and the second word line includes a second doped material having a second impurity concentration in a region having a second width, the second impurity concentration is lower than the first impurity concentration, and the second width is wider than the first width.

15 . The semiconductor device of claim 14 , wherein
the region having the second width in the second word line is adjacent to the active region, and the region having the first width in the first word line is adjacent to the device isolation layer.

16 . The semiconductor device of claim 14 , wherein
the first word line includes a first material layer and a second material layer below the first material layer, the first material layer includes the first doped material, the second material layer includes a conductive material, a resistivity of the conductive material of the second material layer is lower than a resistivity of the first doped material, and the second word line includes a third material layer and a fourth material layer below the third material layer, the third material layer includes the second doped material, and the fourth material layer includes the conductive material.

17 . The semiconductor device of claim 16 , wherein
the first doped material is first doped polycrystalline silicon, and the second doped material is second doped polycrystalline silicon.

18 . The semiconductor device of claim 14 , wherein
a first upper surface of the first word line is located at a different level than a second upper surface of the second word line, and a lower end of the storage node contact is located at a higher level than the first upper surface and the second upper surface.

19 . A semiconductor device comprising:
a substrate including a plurality of active regions, the substrate including gate trenches partially recessed from an upper portion of the substrate and extending in a first horizontal direction; dielectric pat

Assignees

• Samsung Electronics Co Ltd

Inventors

• Ahn Junhyeok
• Lee Myeongdong

Classifications

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/31 Primary

  having a storage electrode stacked over the transistor · CPC title

• H10B12/488 Primary

  Word lines · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H10B12/053 Primary

  the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383) · CPC title