Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2020168611-A1
Application number	US-201916566510-A
Country	US
Kind code	A1
Filing date	Sep 10, 2019
Priority date	Nov 26, 2018
Publication date	May 28, 2020
Grant date	—

Abstract

Semiconductor devices are provided. A semiconductor device includes a substrate including a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other. The semiconductor device includes a gate trench that extends across the plurality of active regions and the isolation region. The semiconductor device includes a gate structure that extends in the gate trench. The semiconductor device includes a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions. The gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.

First claim

1 . A semiconductor device comprising:
a substrate comprising a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other; a gate trench that extends across the plurality of active regions and the isolation region; a gate structure that extends in the gate trench; and a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions, wherein the gate structure has a first width in the direction in each of the plurality of active regions and has a second width in the direction in the isolation region that is different from the first width.

2 . The semiconductor device of claim 1 , wherein the first width is greater than the second width.

3 . The semiconductor device of claim 2 , wherein the first width is about 110% to about 140% of the second width.

4 . The semiconductor device of claim 2 ,
wherein the gate trench comprises a concave sidewall profile in each of the plurality of active regions, wherein the first width is an average value of a plurality of widths in the direction in each of the plurality of active regions, and wherein the second width is an average value of a plurality of widths in the direction in the isolation region.

5 . The semiconductor device of claim 3 , wherein, in each of the plurality of active regions, the gate structure has a convex sidewall profile, based on the concave sidewall profile of the gate trench in each of the plurality of active regions.

6 . The semiconductor device of claim 3 , wherein the gate structure gradually increases or decreases in width in the direction based on a longitudinal position of the gate structure.

7 . The semiconductor device of claim 1 , wherein the gate trench has a first trench width in the direction in each of the plurality of active regions and has a second trench width in the direction in the isolation region that is different from the first trench width.

8 . The semiconductor device of claim 7 , wherein the first trench width is greater than the second trench width.

9 . The semiconductor device of claim 1 , further comprising:
a capacitor that is electrically connected to one of the plurality of active regions at a first location that is adjacent a first side of the gate structure; and a bit line that is electrically connected to the one of the plurality of active regions at a second location that is adjacent a second side of the gate structure that is opposite the first side.

10 . The semiconductor device of claim 1 , wherein a first depth of the gate trench in each of the plurality of active regions is substantially equal to a second depth of the gate trench in the isolation region.

11 . The semiconductor device of claim 1 , wherein a first depth of the gate trench in each of the plurality of active regions is shallower than a second depth of the gate trench in the isolation region.

12 . A semiconductor device comprising:
a substrate comprising a plurality of active regions that extend longitudinally in a first direction and an isolation region that electrically isolates the plurality of active regions from each other; a gate trench that extends across the plurality of active regions and the isolation region; a gate structure that extends in the gate trench; and a gate dielectric layer that is between the gate trench and the gate structure, in each of the plurality of active regions, wherein a width of the gate structure in the first direction gradually increases or decreases based on a longitudinal position of the gate structure.

13 . The semiconductor device of claim 12 ,
wherein the gate structure comprises a word line comprising:
a first portion in one or more of the plurality of active regions; and
a second portion in the isolation region, and
wherein the first portion of the word line is wider, in the first direction, than the second portion of the word line.

14 . The semiconductor device of claim 12 , wherein the gate structure has a convex sidewall profile in each of the plurality of active regions.

15 . The semiconductor device of claim 14 ,
wherein, in the isolation region, the width of the gate structure decreases along a second direction away from one of the plurality of active regions, and wherein the second direction intersects the first direction.

16 . A semiconductor device comprising:
a substrate comprising a plurality of active regions that extend longitudinally in a direction and an isolation region that electrically isolates the plurality of active regions from each other; a first gate trench and a second gate trench that each extend across the plurality of active regions and the isolation region, the first gate trench being adjacent the second gate trench; a first gate structure and a second gate structure that extend in the first gate trench and the second gate trench, respectively; a first gate dielectric layer that is between the first gate trench and the first gate structure, in the plurality of active regions; and a second gate dielectric layer that is between the second gate trench and the second gate structure, in the plurality of active regions, wherein a distance between the first gate structure and the second gate structure in the direction varies based on a longitudinal position of each of the first and second gate structures.

17 . The semiconductor device of claim 16 , wherein the distance between the first gate structure and the second gate structure in the direction gradually varies based on the longitudinal position of each of the first and second gate structures.

18 . The semiconductor device of claim 17 ,
wherein the first gate structure and the second gate structure are separated from each other in the direction by a first distance where the first gate structure and the second gate structure pass through a first of the plurality of active regions, wherein the first gate structure and the second gate structure are separated from each other in the direction by a second distance where the first gate structure passes through a second of the plurality of active regions and the second gate structure passes through the isolation region, and wherein the first distance is shorter than the second distance.

19 . The semiconductor device of claim 16 , wherein a first lowermost level of each of the first and second gate trenches in each of the plurality of active regions is equal to or higher than a second lowermost level of each of the first and second gate trenches in the isolation region.

20 . The semiconductor device of claim 16 , further comprising:
a third gate trench that extends across the isolation region and across a first of the plurality of active regions that the second gate trench extends across; and a third gate structure that extends in the third gate trench, wherein the distance between the first gate structure and the second gate structure in the direction comprises a first distance by which a portion of the first gate structure and a portion of the second gate structure are spaced apart from each other in a second of the plurality of active regions, and wherein a portion of the third gate structure that is in the isolation region is spaced apart from the portion of the first gate structure that is in the second of the plurality of active regions by a second distance in the direction that is longer than the first distance.

21 .- 28 . (canceled)

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeon Jae-Hyeon
• Park Se-Keun
• Park Dong-Sik
• Shin Seok-Ho

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10D64/01324

  characterised by the sectional shape, e.g. T or inverted-T · CPC title

• H01L29/42376

  Electricity · mapped topic

• H01L21/28114

  Electricity · mapped topic

• H01L27/10885

  Electricity · mapped topic