Conductive contact for ion through-substrate via

Patent metadata

Field	Value
Publication number	US-2024170524-A1
Application number	US-202418429535-A
Country	US
Kind code	A1
Filing date	Feb 1, 2024
Priority date	Aug 29, 2019
Publication date	May 23, 2024
Grant date	—

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a first substrate having a front-side and a back-side opposite the front-side. A first doped region is in the first substrate and extends continuously from the front-side to the back-side. A conductive contact is over the first doped region. A conductive layer is between the first doped region and the conductive contact. The first doped region abuts a lower surface and sides of the conductive layer.

First claim

What is claimed is:

1 . An integrated chip, comprising:
a first substrate comprising a front-side and a back-side opposite the front-side; a first doped region in the first substrate and extending continuously from the front-side to the back-side; a conductive contact over the first doped region; and a conductive layer between the first doped region and the conductive contact, wherein the first doped region abuts a lower surface and sides of the conductive layer.

2 . The integrated chip of claim 1 , wherein the first substrate comprises a first material and the conductive contact comprises a second material, wherein the conductive layer comprises the first material and the second material.

3 . The integrated chip of claim 1 , wherein the conductive contact comprises a first contact layer over the first doped region, a second contact layer on the first contact layer, and a third contact layer on the second contact layer, wherein the first, second, and third contact layers comprise conductive materials different from one another.

4 . The integrated chip of claim 3 , wherein the first contact layer comprises a first metal material, the second contact layer comprises a metal nitride material, and the third contact layer comprises a second metal material.

5 . The integrated chip of claim 1 , wherein the conductive layer has an ohmic contact with the first doped region.

6 . The integrated chip of claim 1 , further comprising:
an isolation structure in the first substrate and around the first doped region, wherein the conductive layer is spaced between opposing sidewalls of the isolation structure.

7 . The integrated chip of claim 1 , further comprising:
an interconnect structure over the first substrate and electrically coupled to the conductive contact; a second substrate on the interconnect structure; and a plurality of photodetectors disposed in the second substrate, wherein the plurality of photodetectors comprise a doped photodetector having a first doping type, wherein the first doped region comprises the first doping type.

8 . The integrated chip of claim 1 , further comprising:
a second doped region in the first substrate and on opposing sides of the first doped region, wherein the first doped region and the second doped region comprise different doping types, and wherein the first doped region and the second doped region define a through substrate via (TSV).

9 . The integrated chip of claim 8 , wherein opposing outer sidewalls of the conductive contact are spaced between opposing sides of the second doped region.

10 . An integrated chip, comprising:
a substrate comprising a first surface opposite a second surface; a first through substrate via (TSV) in the substrate; a conductive structure over the second surface and the first TSV; and a silicide layer directly between the first TSV and the conductive structure.

11 . The integrated chip of claim 10 , further comprising:
a first interconnect structure on the first surface of the substrate and comprising a plurality of first conductive interconnects electrically coupled to the first TSV; and a second interconnect structure over the second surface of the substrate and comprising a plurality of second conductive interconnects electrically coupled to the first TSV by way of the conductive structure and the silicide layer.

12 . The integrated chip of claim 10 , wherein the silicide layer extends from the second surface to a point below the second surface.

13 . The integrated chip of claim 10 , further comprising:
a second TSV in the substrate and laterally offset from the first TSV, wherein a conductivity type of the second TSV is different from that of the first TSV.

14 . The integrated chip of claim 13 , wherein the first TSV comprises a first doped region in the substrate and comprising a first doping type, wherein the second TSV comprises a second doped region and a third doped region in the substrate, wherein the third doped region is arranged on opposing sides of the second doped region, wherein the second doped region comprises a second doping type opposite the first doping type and the third doped region comprises the first doping type.

15 . The integrated chip of claim 14 , wherein a width of the third doped region along a first side of the second doped region is less than a width of the first doped region.

16 . The integrated chip of claim 14 , further comprising:
an isolation structure in the substrate and around the second doped region, wherein the third doped region extends from a top surface of the isolation structure to the second surface of the substrate.

17 . The integrated chip of claim 10 , further comprising:
a dielectric structure arranged on the second surface of the substrate, wherein the dielectric structure comprises sidewalls defining a trench over the first TSV; and wherein the conductive structure comprises a first contact layer lining the trench, a second contact layer over the first contact layer, and a conductive body over the second contact layer, wherein the second contact layer extends along sidewalls and a lower surface of the conductive body.

18 . A method for forming an integrated chip, comprising:
forming a through substrate via (TSV) in a substrate, wherein the substrate comprises a front-side and a back-side opposite the front-side; forming a dielectric structure along the back-side of the substrate; forming a conductive structure in the dielectric structure and over the TSV; and forming a silicide layer between the TSV and the conductive structure.

19 . The method of claim 18 , further comprising:
forming an interconnect structure on the front-side of the substrate, wherein the TSV is formed before forming the interconnect structure; and performing a thinning process into the back-side of the substrate, wherein the thinning process exposes a surface of the TSV, wherein the dielectric structure is formed along the surface of the TSV.

20 . The method of claim 18 , wherein the silicide layer is formed after forming the conductive structure.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Min-Ying
• Wu Cheng-Ta
• Tu Yeur-Luen

Classifications

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10W20/20 Primary

  Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] · CPC title

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W20/0265

  characterised by the sidewall insulation · CPC title

• H10W20/217

  comprising ring-shaped isolation structures outside of the via holes · CPC title