Integrated circuit protection using stacked dies

Patent metadata

Field	Value
Publication number	US-2024163092-A1
Application number	US-202217985736-A
Country	US
Kind code	A1
Filing date	Nov 11, 2022
Priority date	Nov 11, 2022
Publication date	May 16, 2024
Grant date	—

Abstract

Stacked integrated circuit devices, chip packages and methods for operating a chip package are described herein that provide an increased level of backside protection from physical attacks that could compromise confidentiality or authentication of the integrated circuit device. In one example, a chip stack includes a sacrificial integrated circuit (IC) die stacked with a primary IC die. The sacrificial IC die includes a first split key information source. The primary IC die has security circuitry configured to generate an encryption key based at least in part on first split key information transmitted from the sacrificial IC die across a die-to-die interface to the primary IC die. Separation of the dies to probe or modify of the primary IC die would cause the destruction of split key information required to operate the functional circuitry of the primary IC die.

First claim

What is claimed is:

1 . A chip stack comprising:
a first integrated circuit (IC) die having a first split key information source; and a second IC die stacked with the first IC die to form a die stack, the second IC die having security circuitry configured to generate an encryption key based at least in part on first split key information transmitted from the first IC die across a die-to-die interface to the second IC die.

2 . The chip stack of claim 1 , wherein the first split key information source comprises:
a first routing extending across the interface connecting the first and second IC dies, the first routing having a first portion disposed in the first IC die, a second portion disposed in the second IC die, and a third portion disposed in the interface; and a first routing integrity circuitry disposed in the second IC die and coupled to the second portion of the first routing, the first routing integrity circuitry configured to output a signal based at least in part on a metric of a physical characteristic of the first routing.

3 . The chip stack of claim 2 , wherein the physical characteristic of the first routing selected from the group consisting of resistance, capacitance, and inductance.

4 . The chip stack of claim 2 , wherein the second portion of the first routing comprises routing residing in a metal layer of the second IC die that is disposed farther from the first IC die than the first routing integrity circuit.

5 . The chip stack of claim 2 , wherein the security circuitry is configured to generate the encryption key based at least in part on the signal output by the first routing integrity circuitry that is based at least in part on the metric of the physical characteristic of the first routing, the security circuitry configured to authenticate the generated encryption key based at least in part on the metric of the physical characteristic of the first routing meeting a predefined value.

6 . The chip stack of claim 1 , wherein the first split key information source comprises:
a first physical unclonable function (PUF) device disposed in the first IC die and coupled through the interface to the second IC die.

7 . The chip stack of claim 6 , wherein the first PUF device is selected from the group consisting of ring-oscillator based PUF device, a static random-access memory (SRAM) based PUF device, a connection mesh, SRAM, and non-volatile memory (NVM).

8 . The chip stack of claim 2 further comprising:
a second split key information source disposed in the first IC die, the second split key information source comprising a first physical unclonable function (PUF) device disposed in the first IC die and coupled through the interface to the second IC die;
first summation circuitry disposed in the second IC die, the first summation circuitry having a first input coupled to the first routing integrity circuit and a second input coupled the first PUF device; and
an encryption key assembly circuitry having first input coupled to an output of the first summation circuitry, the encryption key assembly circuitry located further from the interface than the second portion of the first routing.

9 . The chip stack of claim 8 further comprising:
a third split key information source disposed in the first IC die, the third split key information source comprising a second PUF device disposed in the first IC die and coupled through the interface to the second IC die;
a fourth split key information source disposed in the first IC die, the fourth split key information source comprising:
a second routing extending across the interface connecting the first and second IC dies, the second routing having a first portion disposed in the first IC die, a second portion disposed in the second IC die, and a third portion disposed in the interface; and
a second routing integrity circuitry disposed in the second IC die and coupled to the second portion of the second routing, the second routing integrity circuitry configured to output a signal based at least in part on a metric of a physical characteristic of the second routing; and

second summation circuitry disposed in the second IC die, the second summation circuitry having a first input coupled to the second routing integrity circuit and a second input coupled the second PUF device, the second summation circuitry having an output coupled to the encryption key assembly circuitry.

10 . The chip stack of claim 2 , wherein the second portion of the first routing is dead ended in the first IC die.

11 . A chip package comprising:
a package substrate; a first integrated circuit (IC) die; a second IC die stacked with the first IC die on the package substrate, one of the first or second IC die disposed closer to the package substrate; a first routing extending across an interface connecting the first and second IC dies, the first routing having a first portion disposed in the first IC die, a second portion disposed in the second IC die, and a third portion disposed in the interface; a first routing integrity circuitry disposed in the second IC die and coupled to the second portion of the first routing, the first routing integrity circuitry configured to output a signal based on a metric of a physical characteristic of the first routing, the first routing integrity circuitry residing closer to the interface than at least a portion of the first routing; encryption key assembly circuitry disposed in the second IC die in a location further from the interface than the second portion of the first routing, the encryption key assembly circuitry configured to generate an encryption key based at least in part on the metric of the physical characteristic of the first routing; and authentication circuitry disposed in the second IC die configured to authenticate the encryption key received from the encryption key assembly circuitry based at least in part on the encryption key being based at least in part on the metric of the physical characteristic of the first routing.

12 . The chip package of claim 11 , wherein the physical characteristic of the first routing selected from the group consisting of resistance, capacitance, and inductance.

13 . The chip package of claim 11 , wherein the second IC die is mounted directly on the first IC die.

14 . The chip package of claim 11 further comprising:
first summation circuitry disposed in the second IC die, the first summation circuitry having a first input coupled to the first routing integrity circuit; and
a first physical unclonable function (PUF) device disposed in the first IC die and coupled through the interface to a second input of the first summation circuitry.

15 . The chip package of claim 14 , wherein the first PUF device is selected from the group consisting of ring-oscillator based PUF device, a static random-access memory (SRAM) based PUF device, a connection mesh, SRAM, and non-volatile memory (NVM).

16 . A method for operating a chip package comprising:
obtaining first split key information from a first split key information source across a die-to-die interface connecting first and second IC dies; and enabling operation of functional circuitry in at least one of the first or second IC dies based at least in part on determining that the first split key information meets a first target criteria.

17 . The method of claim 16 , wherein obtaining first split key information further comprises:
obtaining a metric of a physical characteristic of a plurality of routings across extending the interface connecting first and second IC dies.

Assignees

• Xilinx Inc

Inventors

• Wesselkamper James D
• Leboeuf Thomas Paul
• Mcneil Steve E
• Moore Jason J
• Anderson James

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W42/405 Primary

  using active circuits · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title