Solid-state imaging device

Patent metadata

Field	Value
Publication number	US-2024153981-A1
Application number	US-202218549450-A
Country	US
Kind code	A1
Filing date	Feb 8, 2022
Priority date	Mar 15, 2021
Publication date	May 9, 2024
Grant date	—

Abstract

A solid-state imaging device is provided that enables miniaturization of a pixel and improvement in electrical properties of a transistor of a pixel circuit. The solid-state imaging device includes a first semiconductor layer and a second semiconductor layer. In the first semiconductor layer, a pixel including a photoelectric converter is arranged in a matrix along a plane direction. The number of the pixel is two or more. The second semiconductor layer is stacked on the first semiconductor layer on an opposite side to a light-incoming side of the pixel. In the second semiconductor layer, a first transistor electrically coupled to the pixel is provided. A gate lengthwise direction of the first transistor is inclined with respect to an arrangement direction of the pixel.

First claim

What is claimed is:

1 . A solid-state imaging device comprising:
a first semiconductor layer in which a pixel is arranged in a matrix along a plane direction, the pixel including a photoelectric converter, number of the pixel being two or more; and a second semiconductor layer stacked on the first semiconductor layer on an opposite side to a light-incoming side of the pixel and including a first transistor, the first transistor being electrically coupled to the pixel and having a gate lengthwise direction inclined with respect to an arrangement direction of the pixel.

2 . The solid-state imaging device according to claim 1 , wherein
the pixel has a rectangular shape in a plan view, and the gate lengthwise direction of the first transistor is parallel with a diagonal direction of the pixel in the plan view.

3 . The solid-state imaging device according to claim 1 , wherein the first transistor constitutes a pixel circuit coupled to the pixel.

4 . The solid-state imaging device according to claim 3 , wherein the first transistor comprises an amplifier transistor, a selection transistor, a reset transistor, or a floating diffusion conversion gain switching transistor that constitutes the pixel circuit.

5 . The solid-state imaging device according to claim 4 , wherein a gate length of the amplifier transistor is longer than a gate length of the selection transistor or the reset transistor.

6 . The solid-state imaging device according to claim 4 , wherein a plurality of the amplifier transistors is electrically coupled in parallel with respect to one the pixel circuit.

7 . The solid-state imaging device according to claim 1 , further comprising:
a first terminal provided on a side of the first semiconductor layer toward the second semiconductor layer, the first terminal being electrically coupled to the pixel via a first wiring layer; and a second terminal provided on a side of the second semiconductor layer toward the first semiconductor layer, the second terminal being electrically coupled to the first transistor via a second wiring layer and bonded to the first terminal.

8 . The solid-state imaging device according to claim 1 , further comprising a penetrating wiring line penetrating the second semiconductor layer from the first semiconductor layer to electrically couple the pixel and the first transistor to each other.

9 . The solid-state imaging device according to claim 3 , further comprising a third semiconductor layer that is stacked on an opposite side of the second semiconductor layer to the first semiconductor layer and on which a peripheral circuit is mounted, the peripheral circuit including a second transistor and controlling the pixel circuit.

10 . The solid-state imaging device according to claim 9 , wherein a gate lengthwise direction of the second transistor is parallel with the arrangement direction of the pixel.

11 . The solid-state imaging device according to claim 1 , wherein one or more elements selected from among a metal body/dielectric body/semiconductor capacitor, a resistor, and a memory element are further provided in the second semiconductor layer.

12 . The solid-state imaging device according to claim 11 , wherein
the metal body/dielectric body/semiconductor capacitor includes a metal body as a first electrode and a semiconductor as a second electrode, the metal body having a rectangular shape in a plan view, and a centerline of the first electrode is parallel with the gate lengthwise direction of the first transistor.

13 . The solid-state imaging device according to claim 11 , wherein a resistor lengthwise direction of the resistor is parallel with the gate lengthwise direction of the first transistor.

14 . The solid-state imaging device according to claim 11 , wherein
the memory element includes paired main electrodes, a channel formation region provided between the main electrodes, a ferroelectric body provided on the channel formation region, and a gate electrode provided on the ferroelectric body, and a gate lengthwise direction of the memory element is parallel with the gate lengthwise direction of the first transistor.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Oishi Hidetoshi
• Ammo Hiroaki
• Miyake Shinichi

Classifications

• H10F39/811

  Interconnections · CPC title

• H10F39/813

  Electronic components shared by multiple pixels, e.g. one amplifier shared by two pixels · CPC title

• H10F39/809 Primary

  of hybrid image sensors · CPC title

• H10F39/80373 Primary

  characterised by the gate of the transistor · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title