Semiconductor device including transistors sharing gates with structures having reduced parasitic circuit

Patent metadata

Field	Value
Publication number	US-2024153950-A1
Application number	US-202418413869-A
Country	US
Kind code	A1
Filing date	Jan 16, 2024
Priority date	Aug 30, 2017
Publication date	May 9, 2024
Grant date	—

Abstract

A semiconductor device includes a first to sixth regions, a first gate, a first metal contact and a second metal contact. The second region is disposed opposite to the first region with respect to the first gate. The first metal contact couples the first region to the second region. The fourth region is disposed opposite to the third region with respect to the first gate. The second metal contact is coupling the third region to the fourth region. The fifth region is disposed between the first gate and the second region, and is disconnected from the first metal contact and the second metal contact. The sixth region is disposed between the first gate and the first region, and is disconnected from the first metal contact and the second metal contact.

First claim

What is claimed is:

1 . A device, comprising:
a first region, a second region, a third region and a fourth region separated from each other; a first metal contact coupling the first region to the second region; a second metal contact coupling the third region to the fourth region, and isolated from the first metal contact; and a first gate disposed between the first region and the second region, and disposed between the third region and the fourth region.

2 . The device of claim 1 , further comprising:
a second gate disposed between the first region and the first gate, and disposed between the third region and the first gate.

3 . The device of claim 1 , further comprising:
a fifth region disposed between the second region and the first gate, and isolated from the first metal contact, wherein the first region and the fifth region are included in a first active area.

4 . The device of claim 3 , further comprising:
a third metal contact coupled to the fifth region, wherein a part of the third metal contact is interposed between the third region and the fourth region.

5 . The device of claim 4 , further comprising:
a sixth region disposed between the fourth region and the first gate, and electrically isolated from the second metal contact, wherein the third region and the sixth region are included in a second active area.

6 . The device of claim 1 , further comprising:
a third metal contact and a fourth metal contact separated from each other along a direction, wherein the first gate is interposed between the third metal contact and the fourth metal along the direction.

7 . The device of claim 6 , wherein the first metal contact, the second metal contact, the third metal contact and the fourth metal are isolated from each other.

8 . The device of claim 6 , further comprising:
a second gate disposed between the first region and the second region, and disposed between the third region and the fourth region, wherein the third metal contact is interposed between the first gate and the second gate.

9 . A device, comprising:
a first metal contact; a second metal contact separated from the first metal contact; a first gate disposed between a first terminal of the first metal contact and a second terminal of the first metal contact, and disposed between a first terminal of the second metal contact and a second terminal of the second metal contact; and a third metal contact disposed between the first gate and the first terminal of the first metal contact, disposed between the first gate and the first terminal of the second metal contact, and disconnected from each of the first metal contact and the second metal contact.

10 . The device of claim 9 , further comprising:
a fourth metal contact disposed between the third metal contact and the first terminal of the first metal contact, disposed between the third metal contact and the first terminal of the second metal contact, and disconnected from each of the first metal contact, the second metal contact and the third metal contact.

11 . The device of claim 10 , further comprising:
a second gate interposed between the third metal contact and the fourth metal contact.

12 . The device of claim 10 , further comprising:
a first active area coupled to each of the first metal contact, the third metal contact and the fourth metal contact; and a second active area coupled to each of the second metal contact, the third metal contact and the fourth metal contact.

13 . The device of claim 12 , wherein the first gate crosses over each of the first active area and the second active area.

14 . The device of claim 12 , wherein a conductive type of the first active area is different from a conductive type of the second active area.

15 . A device, comprising:
a first transistor, wherein a first terminal of the first transistor is configured to receive a first voltage signal, and a second terminal of the first transistor is configured to receive a second voltage signal through a first resistor; a second transistor, wherein a first terminal of the second transistor is configured to receive the first voltage signal and a control terminal of the second transistor is configured to receive the first voltage signal through a second resistor; and a third transistor, wherein a first terminal of the third transistor is configured to receive the second voltage signal, a second terminal of the third transistor is coupled to a second terminal of the second transistor, and a control terminal of the third transistor is configured to receive the second voltage signal through a third resistor.

16 . The device of claim 15 , further comprising:
a fourth transistor coupled between a control terminal of the first transistor and the first terminal of the third transistor.

17 . The device of claim 16 , wherein a control terminal of the fourth transistor is coupled to the second terminal of the first transistor.

18 . The device of claim 16 , wherein a first terminal of the fourth transistor is configured to receive the first voltage signal through a fourth resistor.

19 . The device of claim 18 , wherein a second terminal of the fourth transistor is configured to receive the second voltage signal.

20 . The device of claim 18 , wherein the control terminal of the first transistor is configured to receive the first voltage signal through the fourth resistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Yi-Feng
• Peng Po-Lin
• Lee Jam-Wem

Classifications

• H10D89/713

  including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D62/371

  Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title