Stacked dies and methods for forming bonded structures

US2024145458A1 · US · A1

Patent metadata
FieldValue
Publication numberUS-2024145458-A1
Application numberUS-202318399478-A
CountryUS
Kind codeA1
Filing dateDec 28, 2023
Priority dateMay 19, 2016
Publication dateMay 2, 2024
Grant date

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated device die can be directly bonded to the first integrated device die without an intervening adhesive.

First claim

Opening claim text (preview).

1 . (canceled) 2 . A bonded structure of stacked dies, comprising: a first integrated device die, wherein the first integrated device die comprises an upper surface opposite a lower surface and a side surface between the upper and lower surfaces of the first integrated device die and wherein the upper surface comprises first conductive features and a first nonconductive region in which the first conductive features are at least partially embedded; a second integrated device die directly bonded to the upper surface of the first integrated device die without an intervening adhesive, wherein the second integrated device die comprises an upper surface opposite a lower surface and a side surface between the lower and upper surfaces of the second integrated device die, wherein the lower surface comprises second conductive features and a second nonconductive region in which the second conductive features are at least partially embedded, and wherein the first conductive features of the first integrated device die are directly bonded to the second conductive features of the second integrated device die and the first nonconductive region of the first integrated device die is directly bonded to the second nonconductive region of the lower surface of the second integrated device die; and a protective material disposed on the side surfaces of the first and second integrated device dies, wherein the protective material has an outer surface characteristic of singulation after forming the protective material and directly bonding the second integrated device die to the upper surface of the first integrated device die. 3 . The bonded structure of claim 2 , wherein the protective material has a coefficient of thermal expansion that is within 10 ppm/° C. of a coefficient of thermal expansion of the first integrated device die. 4 . The bonded structure of claim 2 , wherein the protective material comprises a first protective layer on a side surface of the first integrated device die and a second protective layer on a side surface of the second integrated device die, the first and second protective layers having an interface therebetween. 5 . The bonded structure of claim 2 , wherein the protective material comprises a first layer on the side surfaces of the first and second integrated device dies and a second layer disposed over the first layer. 6 . The bonded structure of claim 2 , wherein the first nonconductive region of the first integrated device die is covalently bonded to the second nonconductive region of the lower surface of the second integrated device die. 7 . The bonded structure of claim 2 , wherein the protective material comprises a polymer material. 8 . The bonded structure of claim 7 , wherein the protective material comprises filler particles within the polymer material. 9 . The bonded structure of claim 7 , wherein the polymer material has a Poisson ratio between 0.4 and 0.5. 10 . The bonded structure of claim 2 , wherein the protective material comprises a first protective material, the bonded structure further comprising: a second protective material disposed over the upper surface of the second integrated device die. 11 . The bonded structure of claim 2 , wherein a thickness of the second integrated device die is less than 40 m. 12 . The bonded structure of claim 2 , wherein the side surfaces of the first and integrated device dies are aligned with each other. 13 . A bonded structure of stacked dies, comprising: a first integrated device die, wherein the first integrated device die comprises an upper surface opposite a lower surface and a side surface between the upper and lower surfaces of the first integrated device die and wherein the upper surface comprises first conductive features and a first nonconductive region in which the first conductive features are at least partially embedded; a second integrated device die directly bonded to the upper surface of the first integrated device die without an intervening adhesive, wherein the second integrated device die comprises an upper surface opposite a lower surface and a side surface between the upper and lower surfaces of the second integrated device die, wherein the lower surface comprises second conductive features and a second nonconductive region in which the second conductive features are at least partially embedded, and wherein the first conductive features of the first integrated device die are directly bonded to the second conductive features of the second integrated device die and the first nonconductive region of the first integrated device die is directly bonded to the second nonconductive region of the lower surface of the second integrated device die; and a protective material disposed on the side surfaces of the first and second integrated device die, wherein the protective material comprises a polymer material. 14 . The bonded structure of claim 13 , wherein the protective material comprises filler particles within the polymer material. 15 . The bonded structure of claim 13 , wherein the protective material has an outer surface characteristic of singulation after forming the protective material and directly bonding the second integrated device die to the upper surface of the first integrated device die. 16 . The bonded structure of claim 13 , wherein the first nonconductive region of the first integrated device die is covalently bonded to the second nonconductive region of the lower surface of the second integrated device die. 17 . The bonded structure of claim 13 , wherein the protective material has a coefficient of thermal expansion that is within 10 ppm/° C. of a coefficient of thermal expansion of the first integrated device die. 18 . The bonded structure of claim 13 , wherein the protective material comprises a first protective layer on a side surface of the first integrated device die and a second protective layer on a side surface of the second integrated device die, the first and second protective layers having an interface therebetween. 19 . The bonded structure of claim 13 , wherein the protective material comprises a first protective material, the bonded structure further comprising: a second protective material disposed over the upper surface of the second integrated device die. 20 . The bonded structure of claim 13 , wherein a thickness of the second integrated device die is less than 40 m. 21 . The bonded structure of claim 13 , wherein the side surfaces of the first and integrated device dies are aligned with each other.

Assignees

Inventors

Classifications

  • for supporting or gripping · CPC title

  • Grinding, lapping or polishing of wafers, substrates or parts of devices · CPC title

  • characterised by their composition, e.g. multilayer masks or materials · CPC title

  • Etching of wafers, substrates or parts of devices · CPC title

  • between stacked chips · CPC title

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What does patent US2024145458A1 cover?
In various embodiments, a method for forming a bonded structure is disclosed. The method can comprise mounting a first integrated device die to a carrier. After mounting, the first integrated device die can be thinned. The method can include providing a first layer on an exposed surface of the first integrated device die. At least a portion of the first layer can be removed. A second integrated…
Who is the assignee on this patent?
Adeia Semiconductor Bonding Technologies Inc
What technology area does this patent fall under?
Primary CPC classification H10W74/014. Mapped technology areas include Electricity.
When was this patent published?
Publication date Thu May 02 2024 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).