Conductive perforated plate for electrical test

Patent metadata

Field	Value
Publication number	US-2024142496-A1
Application number	US-202217975071-A
Country	US
Kind code	A1
Filing date	Oct 27, 2022
Priority date	Oct 27, 2022
Publication date	May 2, 2024
Grant date	—

Abstract

The present disclosure generally relates to a conductive perforated plate for electrical testing of a device under test (DUT) in semiconductor processing. In an example, a device circuit in a die area is formed in or over a semiconductor substrate. The device circuit has an interconnect level. A DUT is formed in or over the semiconductor substrate. A conductive perforated plate is formed in the interconnect level conductively connected to the DUT. A plurality of insulating islands is disposed within the conductive perforated plate.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, the method comprising:
forming a device circuit in a die area in or over a semiconductor substrate, the device circuit having an interconnect level; forming a device under test (DUT) in or over the semiconductor substrate; and forming a conductive perforated plate in the interconnect level conductively connected to the DUT, a plurality of insulating islands being disposed within the conductive perforated plate.

2 . The method of claim 1 , wherein the conductive perforated plate comprises tungsten.

3 . The method of claim 1 , wherein the insulating islands form a hexagonal array.

4 . The method of claim 1 , wherein the DUT extends through and beyond a scribe lane.

5 . The method of claim 1 , wherein a pre-metal dielectric (PMD) layer is located between the conductive perforated plate and the semiconductor substrate.

6 . The method of claim 1 , wherein the conductive perforated plate is formed over and contacting a top-most metal level over the semiconductor substrate.

7 . The method of claim 1 , wherein the conductive perforated plate contacts a metal pad having a perimeter that circumscribes the conductive perforated plate.

8 . The method of claim 1 , wherein the plurality of insulating islands are arranged in an array within the conductive perforated plate.

9 . The method of claim 1 , further comprising forming a scribe seal between the conductive perforated plate and the die area.

10 . The method of claim 1 further comprising:
contacting the conductive perforated plate with a probe pin of a test probe; and
performing an electrical test of the DUT using the conductive perforated plate and the probe pin.

11 . A method of fabricating an integrated circuit, the method comprising:
contacting a perforated metal plate with a probe pin of a test probe, the perforated metal plate being conductively connected to a device under test formed on or over a semiconductor substrate and adjacent a die area of the semiconductor substrate, a plurality of insulating islands being disposed through the perforated metal plate; performing an electrical test of the device under test with the probe pin in contact with the perforated metal plate; and packaging a die comprising the die area.

12 . An integrated circuit, comprising:
a device circuit in a die area in or over a semiconductor substrate, the device circuit having an interconnect level including a dielectric material over the semiconductor substrate; a conductive plate in the interconnect level; and a plurality of insulating islands within the conductive plate, the insulating islands including the dielectric material.

13 . The integrated circuit of claim 12 , wherein the conductive plate is conductively connected to a device under test disposed on or over the semiconductor substrate.

14 . The integrated circuit of claim 12 , wherein the conductive plate comprises tungsten.

15 . The integrated circuit of claim 12 , wherein the plurality of insulating islands within the conductive plate are arranged in a hexagonal array.

16 . The integrated circuit of claim 12 , wherein a pre-metal dielectric (PMD) layer is disposed between the conductive plate and the semiconductor substrate.

17 . The integrated circuit of claim 12 , wherein the dielectric material is disposed over a top-most metal level over the semiconductor substrate.

18 . The integrated circuit of claim 12 , wherein the conductive plate contacts a metal pad in a metal level, the metal pad having a perimeter that circumscribes a perimeter of the conductive plate.

19 . The integrated circuit of claim 12 , wherein the conductive plate is disposed in a remnant scribe lane.

20 . The integrated circuit of claim 12 , further comprising a scribe seal disposed between the conductive plate and the die area.

Assignees

• Texas Instruments Inc

Inventors

• Weiss Wolfgang
• Bayerstadler Anton Johann
• Bakker Peter

Classifications

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H10P74/277 Primary

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G01R1/07342 Primary

  the body of the probe being at an angle other than perpendicular to test object, e.g. probe card · CPC title

• H01L22/14

  Electricity · mapped topic