Error Detection and Recovery When Streaming Data

Patent metadata

Field	Value
Publication number	US-2024134737-A1
Application number	US-202318490675-A
Country	US
Kind code	A1
Filing date	Oct 18, 2023
Priority date	Mar 5, 2021
Publication date	Apr 25, 2024
Grant date	—

Abstract

Systems, apparatuses, and methods for error detection and recovery when streaming data are described. A system includes one or more companion direct memory access (DMA) subsystems for transferring data. When an error is detected for a component of the companion DMA subsystem(s), the operations performed by the other components need to gracefully adapt to this error so that operations face only a minimal disruption. For example, while one or more consumers are still consuming a first frame, a companion router receives an indication of an error for a second frame, causing the companion router to send a router frame abort message to a route manager. In response, the route manager waits until the consumer(s) are consuming the second frame before sending them a frame abort message. The consumer(s) flush their pipeline and transition to an idle state waiting for a third frame after receiving the frame abort message.

First claim

1 .- 20 . (canceled)

21 . A system, comprising:
image generation circuitry configured to generate a plurality of frames; a producer direct memory access (DMA) circuit configured to send the generated plurality of frames to a consumer DMA circuit; and a consumer DMA circuit configured to:
drain credits received from the producer DMA circuit to allow the producer DMA circuit to finish sending a first frame of the plurality of frames without resetting; and
proceed to another frame of the plurality of frames without resetting.

22 . The system of claim 21 , wherein the image generation circuitry is an image signal processor, a camera, an image sensor, or a graphics processing unit (GPU).

23 . The system of claim 21 , wherein the system further comprises a display of a virtual reality headset, wherein the plurality of frames are individually encoded using a streaming codec, and wherein the consumer DMA circuit is configured to send the plurality of frames to the display via codec circuitry that decodes individual frames of the plurality of frames encoded using the streaming codec.

24 . The system of claim 21 , wherein the producer DMA circuit is configured to send, responsive to detecting an error during sending of a second frame of the plurality of frames, dummy data for the second frame to the consumer DMA circuit; and wherein the consumer DMA circuit is configured to finish consuming the dummy data of the second frame without resetting.

25 . The system of claim 21 , further comprising a fabric configured to:
connect to a plurality of DMA circuits including the producer DMA circuit and the consumer DMA circuit; and couple the producer DMA circuit to the consumer DMA circuit.

26 . The system of claim 25 , wherein the fabric connects to individual ones of the plurality of DMA circuits via respective companion wrapper circuits, and wherein individual ones of the companion wrapper circuits are configured to manage flow control for data and credits over the fabric.

27 . The system of claim 26 , further comprising:
a companion router circuit configured to:
couple to the respective companion wrapper circuits of the plurality of DMA circuits to initiate transfers of data;
receive an indication of a second error during transfer of a second frame from the consumer DMA circuit; and
send a frame abort message to a route manager circuit responsive to receiving the indication of the second error during transfer of the second frame; and
the route manager circuit configured to wait, responsive to receiving the frame abort message, until the consumer DMA circuit finishes consuming the first frame and is actively consuming the second frame before forwarding the frame abort message to the consumer DMA circuit.

28 . An apparatus, comprising:
a producer direct memory access (DMA) circuit configured to send a plurality of frames generated by image generation circuitry to a consumer DMA circuit; and a consumer DMA circuit configured to:
drain credits received from the producer DMA circuit to allow the producer DMA circuit to finish sending a first frame of the plurality of frames without resetting; and
proceed to another frame of the plurality of frames without resetting.

29 . The apparatus of claim 28 , wherein the image generation circuitry is an image signal processor, a camera, an image sensor, or a graphics processing unit (GPU).

30 . The apparatus of claim 28 , wherein the producer DMA circuit configured to send, responsive to detecting an error during sending of a second frame of the plurality of frames, dummy data for the second frame to the consumer DMA circuit; and wherein the consumer DMA circuit is configured to finish consuming the dummy data of the second frame without resetting.

31 . The apparatus of claim 30 , wherein the error is a stall waiting for data from the image generation circuitry.

32 . The apparatus of claim 28 , further comprising a fabric configured to:
connect to a plurality of DMA circuits including the producer DMA circuit and the consumer DMA circuit; and couple the producer DMA circuit to the consumer DMA circuit.

33 . The apparatus of claim 32 wherein the fabric connects to individual ones of the plurality of DMA circuits via respective companion wrapper circuits, and wherein individual ones of the companion wrapper circuits are configured to manage flow control for data and credits over the fabric.

34 . The apparatus of claim 33 , further comprising:
a companion router circuit configured to:
couple to the respective companion wrapper circuits of the plurality of DMA circuits to initiate transfers of data;
receive an indication of a second error during transfer of a second frame from the consumer DMA circuit; and
send a frame abort message to a route manager circuit responsive to receiving the indication of the second error during transfer of the second frame; and
the route manager circuit configured to wait, responsive to receiving the frame abort message, until the consumer DMA circuit finishes consuming the first frame and is actively consuming the second frame before forwarding the frame abort message to the consumer DMA circuit.

35 . A method, comprising:
sending, by a producer direct memory access (DMA) circuit, a plurality of frames generated by an image generation circuitry to a consumer DMA circuit; draining credits, by the consumer DMA circuit, received from the producer DMA circuit to allow the producer DMA circuit to finish sending a first frame of the plurality of frames without resetting; and proceeding by the consumer DMA circuit to another frame of the plurality of frames without resetting.

36 . The method of claim 35 , wherein the image generation circuitry is an image signal processor, a camera, an image sensor, or a graphics processing unit (GPU).

37 . The method of claim 35 , further comprising:
sending, by the producer DMA circuit responsive to detecting a stall waiting for data from the image generation circuitry during sending of a second frame of the plurality of frames, dummy data for the second frame to the consumer DMA circuit; and finish consuming, by the consumer DMA circuit, the dummy data of the second frame without resetting.

38 . The method of claim 35 , further comprising transmitting data from the producer DMA circuit to the consumer DMA circuit over a fabric connecting a plurality of DMA circuits including the producer DMA circuit and the consumer DMA circuit.

39 . The method of claim 38 , comprising managing flow control for data and credits over the fabric by respective companion wrapper circuits of individual ones of the plurality of DMA circuits.

40 . The method of claim 39 , comprising:
performing by a companion router circuit:
coupling to the respective companion wrapper circuits of the plurality of DMA circuits to initiate transfers of data;
receiving an indication of an error during transfer of a second frame from the consumer DMA circuit; and
sending a frame abort message to a route manager circuit responsive to receiving the indication of the second error during transfer of the second frame; and
waiting, by the route manager circuit responsive to receiving the frame abort message, until the consumer DMA circuit finishes consuming the first frame and is actively consuming the second frame before forwarding the frame abort message to the consumer DMA circuit.

Assignees

• Apple Inc

Inventors

• Schaub Marc A
• Moss Roy G
• Bekerman Michael

Classifications

• G06F11/0793 Primary

  Remedial or corrective actions (recovery from an exception in an instruction pipeline G06F9/3861; by retry G06F11/1402; for recovering from a failure of a protocol instance or entity H04L69/40) · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title