System and method for device synchronization

Patent metadata

Field	Value
Publication number	US-11200182-B1
Application number	US-201916411500-A
Country	US
Kind code	B1
Filing date	May 14, 2019
Priority date	May 14, 2019
Publication date	Dec 14, 2021
Grant date	Dec 14, 2021

Abstract

A system includes a synchronizer circuit configured to monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device. The synchronizer circuit monitors a second bus between the memory and a second device to receive a first read transaction of a read request from the second device. The synchronizer circuit determines that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory. In response to the determination, the first read transaction is sent to the memory.

First claim

What is claimed is:

1. A system, comprising:
a synchronizer circuit configured to:
monitor a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device, wherein the determining the occupancy threshold includes:
updating the occupancy threshold based on one or more write transactions of a first write request detected on the first bus;

monitor a second bus between the memory and a second device to receive a first read transaction of a read request from the second device;
determine that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory,
wherein in response to the determination, the first read transaction is sent to the memory.

2. The system of claim 1 , wherein to monitor the first bus to determine the occupancy threshold of the memory, for each write transaction of the first write request detected on the first bus, the synchronizer circuit is configured to:
determine a transaction size of the write transaction; and
update the occupancy threshold based on the transaction size.

3. The system of claim 2 , wherein the first read transaction is associated with a frame read request for reading a first frame of a video from the memory, and
wherein the first read transaction starts to perform reading from the memory before the first frame is completely written to the memory.

4. The system of claim 2 , wherein each write transaction is associated with a frame write request for writing a frame to the memory, and
wherein the frame write request includes a plurality of write transactions for writing portions of the frame to the memory respectively.

5. The system of claim 2 , wherein the first bus is an Advanced Extensible Interface (AXI) bus, and
wherein the transaction size of the write transaction is determined based on a burst number indicating a number of data transfers in the write transaction.

6. The system of claim 1 , wherein the synchronizer circuit is configured to:
store the first read transaction in a first-in-first-out (FIFO) buffer;
in response to the determination that the first read transaction is allowed to be sent to the memory, retrieve a second read transaction from the FIFO buffer and send the retrieved second read transaction to the memory.

7. The system of claim 6 , wherein the synchronizer circuit is configured to:
in response to a determination that the second read transaction is not allowed to be sent to the memory based on the occupancy threshold of the memory, blocking the second read transaction from being sent to the memory.

8. The system of claim 1 , wherein the first device includes a capture device for capturing a plurality of frames of a video and storing the plurality of frames in the memory, and
wherein the second device includes an encoder device for retrieving the plurality of frames from the memory and encoding the plurality of frames.

9. The system of claim 1 , wherein the first device includes a decoder device for decoding encoded frames of a video and storing the decoded frames in the memory, and
wherein the second device includes a display device for retrieving the decoded frames from the memory for display.

10. The system of claim 9 , further comprising:
a capture device for capturing a plurality of frames of a video and storing the plurality of frames in the memory;
an encoder device for retrieving the plurality of frames from the memory and encoding the plurality of frames; and
a capture-encode synchronizer circuit configured to monitor third and fourth buses for scheduling one or more read transactions from the encoder device,
wherein the memory is coupled to the capture device and encoder device using the third and fourth buses respectively.

11. A method, comprising:
monitoring a first bus coupled between a memory and a first device to determine an occupancy threshold of the memory based on one or more write requests from the first device,
wherein the determining the occupancy threshold includes:
updating the occupancy threshold based on one or more write transactions of a first write request detected on the first bus;

monitoring a second bus between the memory and a second device to receive a first read transaction of a read request from the second device;
determining that the first read transaction is allowed to be sent to the memory based on the occupancy threshold of the memory; and
in response to the determination, sending the first read transaction to the memory.

12. The method of claim 11 , wherein the monitoring the first bus to determine the occupancy threshold of the memory includes:
for each write transaction detected on the first bus,
determining a transaction size of the write transaction; and
updating the occupancy threshold based on the transaction size.

13. The method of claim 12 , wherein the first read transaction is associated with a frame read request for reading a first frame of a video from the memory, further comprising:
starting to read data associated with the first read transaction from the memory before the first frame is completely written to the memory.

14. The method of claim 12 , wherein each write transaction is associated with a frame write request for writing a frame to the memory, and
wherein the frame write request includes a plurality of write transactions for writing portions of the frame to the memory respectively.

15. The method of claim 12 , wherein the first bus is an Advanced Extensible Interface (AXI) bus, and
wherein the transaction size of the write transaction is determined based on a burst number indicating a number of data transfers in the write transaction.

16. The method of claim 11 , further comprising:
storing the first read transaction in a first-in-first-out (FIFO) buffer;
in response to the determination that the first read transaction is allowed to be sent to the memory, retrieving a second read transaction from the FIFO buffer and sending the retrieved second read transaction to the memory.

17. The method of claim 16 , further comprising:
in response to a determination that the second read transaction is not allowed to be sent to the memory based on the occupancy threshold of the memory, blocking the second read transaction from being sent to the memory.

18. The method of claim 11 , wherein the first device includes a capture device for capturing a plurality of frames of a video and storing the plurality of frames in the memory, and
wherein the second device includes an encoder device for retrieving the plurality of frames from the memory and encoding the plurality of frames.

19. The method of claim 11 , wherein the first device includes a decoder device for decoding encoded frames of a video and storing the decoded frames in the memory, and
wherein the second device includes a display device for retrieving the decoded frames from the memory for display.

20. The method of claim 19 , further comprising:
capturing, by a capture device, a plurality of frames of a video and storing the plurality of frames in the memory;
retrieving, by an encoder device, the plurality of frames from the memory and encoding the plurality of frames; and
monitoring third and fourth buses for scheduling one or more read transactions from the encoder device, wherein the memory is coupled to the capture device and encoder device using the third and fourth buses respectively.

Assignees

• Xilinx Inc

Inventors

• Sarmah Mrinal J
• Manjunath Shreyas
• Raha Prasun K

Classifications

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F13/161

  with latency improvement · CPC title

• G06F2213/16

  Memory access · CPC title

• G06F9/467

  Transactional memory (G06F9/528 takes precedence) · CPC title