Metal chalcogenide thin film, thin-film transistor including the same, and method of manufacturing the thin-film transistor

Patent metadata

Field	Value
Publication number	US-2024128421-A1
Application number	US-202318364399-A
Country	US
Kind code	A1
Filing date	Aug 2, 2023
Priority date	Oct 18, 2022
Publication date	Apr 18, 2024
Grant date	—

Abstract

A display device includes: a substrate; a thin-film transistor on the substrate; and a light-emitting diode electrically connected to the thin-film transistor, wherein the thin-film transistor includes: a semiconductor layer in which a source region, a drain region, and a channel region are defined; a gate electrode insulated from the semiconductor layer and overlapping the semiconductor layer; a source electrode electrically connected to the source region; and a drain electrode electrically connected to the drain region, wherein the semiconductor layer includes a crystallized metal chalcogenide including a transition metal and a chalcogen element and has a layered structure.

First claim

What is claimed is:

1 . A display device comprising:
a substrate; a thin-film transistor on the substrate; and a light-emitting diode electrically connected to the thin-film transistor, wherein the thin-film transistor comprises:
a semiconductor layer in which a source region, a drain region, and a channel region are defined;
a gate electrode insulated from the semiconductor layer and overlapping the semiconductor layer;
a source electrode electrically connected to the source region; and
a drain electrode electrically connected to the drain region,
wherein the semiconductor layer,
comprises a crystallized metal chalcogenide comprising a transition metal and a chalcogen element, and
has a layered structure.

2 . The display device of claim 1 , wherein the transition metal comprises at least one of bismuth (Bi), tin (Sn), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), hafnium (Hf), titanium (Ti), or rhenium (Re), and the chalcogen element comprises at least one of sulfur (S), selenium (Se), or tellurium (Te).

3 . The display device of claim 2 , wherein the semiconductor layer comprises bismuth sulfide (Bi 2 S 3 ).

4 . The display device of claim 1 , wherein the layered structure of the semiconductor layer has a structure in which a first sub-layer and a second sub-layer are alternately stacked.

5 . The display device of claim 4 , wherein the transition metal of the crystallized metal chalcogenide is arranged in the first sub-layer, and the chalcogen element of the crystallized metal chalcogenide is arranged in the second sub-layer.

6 . The display device of claim 1 , wherein, in the crystallized metal chalcogenide, a main peak obtained by an X-ray diffraction (XRD) spectrum is in a region where a diffraction angle 2θ is about 15° to about 16°, and a sub-peak obtained by the X-ray diffraction (XRD) spectrum is in a region where the diffraction angle 2θ is about 25° to about 26°.

7 . The display device of claim 1 , wherein the semiconductor layer has a thickness of about 10 nm to about 50 nm.

8 . The display device of claim 1 , wherein electron mobility of the thin-film transistor comprising the semiconductor layer has a value of about 10 cm 2 V −1 s −1 to about 14 cm 2 V −1 s −1 .

9 . The display device of claim 1 , wherein an on-to-off current ratio of the thin-film transistor comprising the semiconductor layer has a value of about 10 4 to about 10 9 .

10 . The display device of claim 1 , wherein the semiconductor layer has a band gap of about 1.4 eV to about 1.6 eV.

11 . The display device of claim 1 , wherein the semiconductor layer has a surface roughness of about 0.23 nm to about 0.25 nm.

12 . A method of manufacturing the display device of claim 1 , the method comprising:
forming the thin-film transistor on the substrate; and forming the light-emitting diode electrically connected to the thin-film transistor, wherein the forming of the thin-film transistor comprises:
forming the semiconductor layer in which the source region, the drain region, and the channel region are defined;
forming the gate electrode insulated from the semiconductor layer and overlapping the semiconductor layer;
forming the source electrode electrically connected to the source region; and
forming the drain electrode electrically connected to the drain region,
wherein the forming of the semiconductor layer comprises:
depositing a semiconductor precursor comprising a metal chalcogenide, which comprises the transition metal and the chalcogen element; and
crystallizing the semiconductor precursor to have the layered structure.

13 . The method of claim 12 , wherein the metal chalcogenide is a compound of a transition metal and a chalcogen element, and
wherein the transition metal comprises at least one of bismuth (Bi), tin (Sn), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), hafnium (Hf), titanium (Ti), or rhenium (Re), and the chalcogen element comprises at least one of sulfur (S), selenium (Se), or tellurium (Te).

14 . The method of claim 13 , wherein the semiconductor layer having the layered structure comprises bismuth sulfide (Bi 2 S 3 ).

15 . The method of claim 12 , wherein the depositing of the semiconductor precursor is performed through a thermal deposition process.

16 . The method of claim 15 , wherein the thermal deposition process comprises:
providing a thermal deposition source and the substrate into a vacuum chamber; heating the thermal deposition source; and evaporating a material included in the thermal deposition source, in an atomic or molecular state, and depositing the material on a surface of the substrate to coat the surface of the substrate with a thin film.

17 . The method of claim 16 , wherein the thermal deposition source comprises Bi metal and Bi 2 S 3 powder.

18 . The method of claim 16 , wherein, in the thermal deposition process, an inside of the vacuum chamber is heated to and then maintained at about 150° C. to about 450° C.

19 . The method of claim 12 , wherein the semiconductor layer has a thickness of about 10 nm to about 50 nm.

20 . The method of claim 12 , wherein the crystallizing of the semiconductor precursor is performed through a heat treatment process.

21 . The method of claim 20 , wherein the heat treatment process comprises applying heat of about 100° C. to about 150° C. for about 30 minutes to about 1 hour.

22 . The method of claim 12 , wherein, through the crystallizing of the semiconductor precursor, electron mobility of the thin-film transistor has a value of about 10 cm 2 V −1 s −1 to about 14 cm 2 V −1 s −1 .

23 . The method of claim 12 , wherein, through the crystallizing of the semiconductor precursor, an on-to-off current ratio of the thin-film transistor has a value of about 10 4 to about 10 9 .

Assignees

• Samsung Display Co Ltd
• Postech Res & Business Dev Found

Inventors

• Kim Hyungjun
• Noh Yongyoung
• LIM Junhyung
• Liu Ao

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10D62/402

  Amorphous materials · CPC title

• H10D62/84

  being selenium or tellurium only · CPC title