Apparatus for processing plasma and method of processing plasma and manufacturing semiconductor device using the same

Patent metadata

Field	Value
Publication number	US-2024128055-A1
Application number	US-202318232992-A
Country	US
Kind code	A1
Filing date	Aug 11, 2023
Priority date	Oct 18, 2022
Publication date	Apr 18, 2024
Grant date	—

Abstract

A method of manufacturing a semiconductor device includes placing a wafer in a plasma chamber, the chamber including a first power generator configured to generate plasma ions in the chamber, and a second power generator configured to accelerate the plasma ions toward the wafer, generating a radio frequency (RF) signal having a repeated periodic sinusoidal waveform in an on state and a steady off state by the first power generator, and generating a direct current (DC) bias signal having a repeated periodic non-sinusoidal waveform in an on state and a steady off state by the second power generator. The RF signal and the DC bias signal are offset from each other. The method further includes performing a plasma process on a layer on the wafer, using the RF signal and DC bias signal.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device, comprising:
placing a wafer in a plasma chamber, the chamber including:
a first power generator configured to generate plasma ions in the chamber, and
a second power generator configured to accelerate the plasma ions toward the wafer;
generating a radio frequency (RF) signal having a repeated periodic sinusoidal waveform in an on state and a steady off state by the first power generator, and generating a direct current (DC) bias signal having a repeated periodic non-sinusoidal waveform in an on state and a steady off state by the second power generator, wherein the RF signal and the DC bias signal are offset from each other; and performing a plasma process on a layer on the wafer, using the RF signal and DC bias signal.

2 . The method of claim 1 , wherein time points when the RF signal and the DC bias signal are respectively turned on are different from each other, and/or time points when the RF signal and the DC bias signal are respectively turned off are different from each other.

3 . The method of claim 1 , wherein time points when the RF signal is turned on and the DC bias signal is turned off are different from each other, and/or time points when the RF signal is turned off and the DC bias signal is turned on are different from each other.

4 . The method of claim 1 , wherein the RF signal is turned on while the DC bias signal is in an on duty, and is turned off while the DC bias signal is in an off duty.

5 . The method of claim 1 , wherein the RF signal is turned on while the DC bias signal is in an off duty.

6 . The method of claim 1 , wherein the second power generator is configured to generate a voltage less than or equal to a reference voltage.

7 . The method of claim 1 , wherein the second power generator is configured to alternately generate, during an on duty, a voltage greater than a reference voltage and a voltage less than the reference voltage.

8 . The method of claim 1 , wherein the RF signal consecutively turns on and turns off while the DC bias signal is in an on duty, and is in an off duty while the DC bias signal is in an off duty.

9 . A method of manufacturing a semiconductor device using a chamber in which a plasma process is performed, the method comprising:
placing a wafer on a bottom electrode located inside the chamber; generating a first reference voltage in a first time section and first power in a second time section and applying the first reference voltage and first power to the bottom electrode; and generating a second reference voltage in a third time section and second power in a fourth time section and applying the second reference voltage and the second power to the bottom electrode, wherein: the first and second time sections arrive alternately and repeatedly, and form a first steady signal alternating with an RF signal; the third and fourth time sections arrive alternately and repeatedly, overlap the first and second time sections, and form a second steady signal alternating with a periodic signal; the second power is generated as a signal having a non-sinusoidal waveform, and the second reference voltage in the third time section and second power in the fourth time section form a direct current (DC) bias signal, and the first reference voltage in the first time section and first power in the second time section form a radio frequency (RF) signal, and the RF signal and the DC bias signal are offset from each other.

10 . The method of claim 9 , wherein the second time section overlaps the third time section.

11 . The method of claim 9 , wherein a length of each of the first and second time sections is different from a length of the third time section.

12 . The method of claim 9 , wherein lengths of the first to fourth time sections are the same.

13 . The method of claim 9 , wherein the second power is generated by a power generator that comprises at least one pulse module configured to generate a square wave and at least one slope module configured to generate a variable waveform, and
the DC bias signal has a set waveform corresponding to a sum of the square wave and the variable waveform.

14 . The method of claim 9 , wherein the second time section overlaps 1% to 99% of the fourth time section.

15 . The method of claim 9 , further comprising a filter connected between the bottom electrode and an output terminal of a second power generator that generates the second power, and configured to block the first power, which is generated by a first power generator connected to the bottom electrode, and to allow the second power to pass through the filter, wherein the filter comprises at least one of a low pass filter, a high pass filter, a band pass filter, and a band stop filter.

16 . The method of claim 9 , wherein the DC bias signal has a frequency selected from a range from 1 kHz to 1 MHz.

17 . A method manufacturing a semiconductor device, the method comprising:
placing a wafer in a chamber; generating first power to generate plasma in the chamber; generating second power to control ion energy of the plasma; and applying the first and second powers to the chamber to perform a plasma process on the wafer, wherein the first power comprises a radio frequency (RF) signal, the second power includes a direct current (DC) bias signal, the second power has a non-sinusoidal waveform, and the RF signal and the DC bias signal are applied at the same time in the chamber and are offset from each other.

18 . The method of claim 17 , wherein the generating of the second power comprises:
generating a square wave to provide a voltage level determined based on a target size of the ion energy; generating a variable waveform determined based on a target distribution of the ion energy; and providing the second power having a set waveform by combining the square wave and the variable waveform.

19 . The method of claim 17 , wherein, in a time section in which the first power is in an on duty, the second power repeats turning on and turning off.

20 . The method of claim 17 , wherein the first power is applied to a bottom electrode or a top electrode of the chamber, and
the second power is applied to the top electrode of the chamber.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Hyunbae
• Kim Jihwan
• Nam Sangki
• Son Daeun
• Shim Seungbo
• Lee Juho
• Lee Hyunjae
• Jeong Hyunhak

Classifications

• H01J37/32174 Primary

  Circuits specially adapted for controlling the RF discharge · CPC title

• H01J37/32128

  using particular waveforms, e.g. polarised waves · CPC title

• H01J2237/0473

  accelerating · CPC title

• H01J37/32146

  Amplitude modulation, includes pulsing · CPC title

• H01J37/32706

  Polarising the substrate · CPC title