Automatic Test Pattern Generation-Based Circuit Verification Method and Apparatus

Patent metadata

Field	Value
Publication number	US-2024125850-A1
Application number	US-202318397481-A
Country	US
Kind code	A1
Filing date	Dec 27, 2023
Priority date	Jun 28, 2021
Publication date	Apr 18, 2024
Grant date	—

Abstract

An automatic test pattern generation-based circuit verification method, comprises: determining a to-be-detected first logic cone from a fan-out logic cone corresponding to the target line; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line; generating a first CNF based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.

First claim

What is claimed is:

1 . An automatic test pattern generation-based circuit verification method, wherein the method comprises:
determining a to-be-detected first logic cone from a fan-out logic cone corresponding to a target line, wherein the fan-out logic cone is a region formed by a gate circuit that passes from the target line to an output end of the circuit under test; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line, wherein the fan-in logic cone is a region formed by a gate circuit that passes from an input end of the circuit under test to the target line, and the second logic cone is a region that is in the fan-in logic cone and that is formed by a gate circuit that affects an output value of the first logic cone; generating a first conjunctive normal form (CNF) based on the first logic cone and the second logic cone, and detecting the target line by using the first CNF to obtain a first detection result, wherein the first detection result indicates a fault type of the target line; and if the first logic cone is a partial region in the fan-out logic cone, and the first detection result meets a first specified condition corresponding to the first logic cone, determining a first verification result of the target line based on the first detection result.

2 . The method according to claim 1 , wherein the method further comprises: if the first logic cone is an entire region of the fan-out logic cone, determining the first verification result based on the first detection result.

3 . The method according to claim 1 , wherein the method further comprises: if the first logic cone is the partial region in the fan-out logic cone, and the first detection result does not meet the first specified condition, determining a to-be-detected first logic cone from the fan-out logic cone again, wherein first logic cones determined different times are not all the same.

4 . The method according to claim 1 , wherein the determining a to-be-detected first logic cone from a fan-out logic cone corresponding to a target line comprises: determining, based on a preset initial depth value and a first step value, the first logic cone from the fan-out logic cone, wherein the initial depth value represents a distance between the target line and the gate circuit.

5 . The method according to claim 4 , wherein the first specified condition is that the fault type in the first detection result is a difficult-to-detect fault.

6 . The method according to claim 1 , wherein the determining a to-be-detected first logic cone from a fan-out logic cone corresponding to a target line comprises: determining, based on a preset quantity of output ends and a second step value, the first logic cone from the fan-out logic cone.

7 . The method according to claim 6 , wherein the first detection result comprises
the fault type and a test pattern, and the test pattern is used to perform circuit fault detection on the circuit under test; and the first specified condition is that the fault type in the first detection result is a detectable fault.

8 . The method according to claim 1 , wherein the method further comprises:
determining a to-be-detected third logic cone from the fan-out logic cone; and determining a to-be-detected fourth logic cone from the fan-in logic cone, wherein the third logic cone is different from the first logic cone, and the fourth logic cone is a region that is in the fan-in logic cone and that is formed by a gate circuit that affects an output value of the third logic cone; generating a second CNF based on the third logic cone and the fourth logic cone, and detecting the target line by using the second CNF to obtain a second detection result, wherein the second detection result indicates the fault type of the target line;
when the first verification result is not determined, if the third logic cone is a partial region in the fan-out logic cone, and the second detection result meets a second specified condition corresponding to the third logic cone, determining a second verification result corresponding to the target line based on the second detection result, and stopping detecting the target line by using the first CNF; and
when the first verification result is determined, stopping detecting the target line by using the second CNF.

9 . The method according to claim 1 , wherein the first CNF comprises at least one clause, and the at least one clause is generated based on a gate circuit in the first logic cone and a gate circuit in the second logic cone.

10 . The method according to claim 9 , wherein the detecting the target line by using the first CNF comprises:
if a quantity of clauses comprised in the first CNF is greater than or equal to a specified threshold, separately performing satisfiability SAT solution on the at least one clause, and determining an SAT solution result of each clause; and using an intersection of SAT solution results of the at least one clause as the first detection result.

11 . The method according to claim 9 , wherein the first CNF comprises at least one target clause corresponding to at least one target subcircuit in the first logic cone and at least one target clause corresponding to at least one target subcircuit in the second logic cone, wherein the target subcircuit is in a one-to-one correspondence with the target clause, and any target subcircuit comprises at least one gate circuit.

12 . The method according to claim 11 , wherein before the determining a to-be-detected first logic cone from a fan-out logic cone corresponding to a target line, the method further comprises:
if a quantity of gate circuits comprised in the fan-in logic cone and the fan-out logic cone is greater than a first specified threshold, determining a target subcircuit in the fan-in logic cone based on the gate circuit in the fan-in logic cone, and determining a target subcircuit in the fan-out logic cone based on the gate circuit in the fan-out logic cone.

13 . The method according to claim 11 , wherein the target subcircuit is a fan-out free region FFR.

14 . The method according to claim 9 , wherein before the determining a to-be-detected first logic cone from a fan-out logic cone corresponding to a target line, the method further comprises: if a quantity of gate circuits comprised in the fan-in logic cone and the fan-out logic cone is greater than a second specified threshold, simplifying two equivalent gate circuits in the fan-in logic cone and the fan-out logic cone into one gate circuit for generating a CNF clause, wherein the second specified threshold is less than the first specified threshold, and the two equivalent gate circuits are two gate circuits with the same input and the same output.

15 . An automatic test pattern generation apparatus, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, and the at least one processor is configured to read a computer program stored in the at least one memory, to perform the following steps:
determining a to-be-detected first logic cone from a fan-out logic cone corresponding to a target line, wherein the fan-out logic cone is a region formed by a gate circuit that passes from the target line to an output end of the circuit under test; determining, based on the first logic cone, a to-be-detected second logic cone from a fan-in logic cone corresponding to the target line, wherein the fan-in logic cone is a region formed by a gate circuit that passes from an input end of the circuit under test to the target line, and

Assignees

• Huawei Tech Co Ltd

Inventors

• Zhen Huiling
• Chen Miaohui
• Yuan Mingxuan
• Wang Naixing
• Luo Wanqian
• Huang Yu

Classifications

• G06F30/33

  Design verification, e.g. functional simulation or model checking · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G01R31/318502

  Test of Combinational circuits · CPC title

• G01R31/31835

  Analysis of test coverage or failure detectability · CPC title

• G01R31/31707

  Test strategies (methods for generation of test sequences G01R31/318371) · CPC title