Memory array utilizing bitcells with single-ended read circuitry

Patent metadata

Field	Value
Publication number	US-2024118826-A1
Application number	US-202217963313-A
Country	US
Kind code	A1
Filing date	Oct 11, 2022
Priority date	Oct 11, 2022
Publication date	Apr 11, 2024
Grant date	—

Abstract

A memory device includes at least one bitcell coupled to a local bitline. The at least one bitcell includes multiple sets of a plurality of transistor devices. The first set of the plurality of transistor devices is configured to form a single write (1W) port for receiving digital data. The second set of the plurality of transistor devices is configured as an inverter pair. The inverter pair stores the digital data. The third set of the plurality of transistor devices is configured to form a single read (1R) port. The 1R port can be used to access the digital data stored at the inverter pair and output the digital data on the local bitline. The plurality of transistor devices includes an equal number of P-channel transistor devices and N-channel transistor devices.

First claim

What is claimed is:

1 . A memory device comprising:
at least one bitcell coupled to a local bitline, the at least one bitcell comprising:
a first set of a plurality of transistor devices configured to form a single write (1W) port, the 1W port to receive digital data;
a second set of the plurality of transistor devices configured as an inverter pair, the inverter pair to store the digital data; and
a third set of the plurality of transistor devices configured to form a single read (1R) port, the 1R port to access the digital data stored at the inverter pair and output the digital data on the local bitline, and the plurality of transistor devices consisting of an equal number of P-channel transistor devices and N-channel transistor devices.

2 . The memory device of claim 1 , wherein the plurality of transistor devices consists of four N-channel metal-oxide semiconductor (NMOS) transistors and four P-channel metal-oxide semiconductor (PMOS) transistors.

3 . The memory device of claim 2 , wherein the first set of the plurality of transistor devices consists of a first NMOS transistor of the four NMOS transistors and a first PMOS transistor of the four PMOS transistors.

4 . The memory device of claim 3 , wherein the 1W port is formed by drain terminals of the first NMOS transistor and the first PMOS transistor.

5 . The memory device of claim 4 , wherein a gate terminal of the first NMOS transistor forms a write-wordline (wwl) terminal and a gate terminal of the first PMOS transistor forms a write-wordline-bar (wwl_b) terminal, the wwl terminal and the wwl_b terminal associated with writing the digital data into the inverter pair.

6 . The memory device of claim 3 , wherein the third set of the plurality of transistor devices consists of a second NMOS transistor of the four NMOS transistors and a second PMOS transistor of the four PMOS transistors.

7 . The memory device of claim 6 , wherein the 1R port is formed by drain terminals of the second NMOS transistor and the second PMOS transistor.

8 . A memory device comprising:
a first plurality of bitcells coupled via a first local bitline (LBL); a second plurality of bitcells coupled via a second LBL, each bitcell of the plurality of bitcells and the second plurality of bitcells comprising a single read (1R) port and a single write (1W) port; and read merge circuitry coupled to the first LBL and the second LBL, the read merge circuitry to perform operations comprising:
pre-charging a node of the first LBL to a first supply voltage;
pre-discharging a node of the second LBL to a second supply voltage;
activating an equalization path between the first LBL and the second LBL, the activating of the equalization path causing charge sharing between the node of the first LBL and the node of the second LBL;
detecting a read wordline (RWL) for a selected bitcell of the first plurality of bitcells or the second plurality of bitcells; and
performing a read operation of the selected bitcell based on the detecting of the RWL.

9 . The memory device of claim 8 , wherein the read merge circuitry further comprises:
a P-channel metal-oxide semiconductor (PMOS) transistor configured as a pre-charge device.

10 . The memory device of claim 9 , wherein the pre-charge device is configured to perform the pre-charging of the node of the first LBL to the first supply voltage during a pre-charging phase of the read merge circuitry.

11 . The memory device of claim 10 , wherein the read merge circuitry further comprises:
a first N-channel metal-oxide semiconductor (NMOS) transistor configured as a pre-discharge device.

12 . The memory device of claim 11 , wherein the pre-discharge device is configured to perform the pre-discharging of the node of the second LBL to the second supply voltage during the pre-charging phase of the read merge circuitry.

13 . The memory device of claim 11 , wherein the read merge circuitry further comprises:
a first equalizing device coupled to the node of the first LBL; and a second equalizing device coupled to the node of the second LBL, wherein the first equalizing device and the second equalizing device are further coupled to each other to form the equalization path.

14 . The memory device of claim 13 , wherein the first equalizing device comprises a second NMOS transistor, the second equalizing device comprises a third NMOS transistor, and wherein a gate of the second NMOS transistor is coupled to a gate of the first NMOS transistor.

15 . The memory device of claim 14 , wherein to activate the equalization path, the read merge circuitry further performs operations comprising:
asserting a first clock signal at the gate of the second NMOS transistor and the gate of the first NMOS transistor to activate the first equalizing device and deactivate the pre-charge device.

16 . The memory device of claim 15 , wherein to activate the equalization path, the read merge circuitry further performs operations comprising:
asserting a buffered version of a second clock signal at the gate of the third NMOS transistor, the second clock signal being asserted at a gate of the first NMOS transistor.

17 . The memory device of claim 8 , wherein the read merge circuitry further comprises:
a feed-forward multiplexing inverter coupled to the first LBL and the second LBL, the feed-forward multiplexing inverter comprising a global bitline (GBL) configured to receive digital data from one the first plurality of bitcells via the first LBL or from one of the second plurality of bitcells via the second LBL.

18 . A memory device comprising:
a first plurality of bitcells coupled via a first local bitline (LBL); a second plurality of bitcells coupled via a second LBL, each bitcell of the plurality of bitcells and the second plurality of bitcells comprising a single read (1R) port and a single write (1W) port; and read merge circuitry coupled to the first LBL and the second LBL, the read merge circuitry comprising:
a pre-charge device coupled to the first LBL, the pre-charge device configured to pre-charge a node of the first LBL to a first supply voltage during a pre-charging phase of the read merge circuitry;
a pre-discharge device coupled to the second LBL, the pre-discharge device configured to pre-discharge a node of the second LBL to a second supply voltage during the pre-charging phase; and
an equalization path configured between the first LBL and the second LBL, the equalization path causing prior to a read operation, charge sharing between the node of the first LBL and the node of the second LBL and equalizing a voltage on the first LBL and a voltage on the second LBL to a voltage level between the first supply voltage and the second supply voltage.

19 . The memory device of claim 18 , wherein the pre-charge device is a P-channel metal-oxide semiconductor (PMOS) transistor, and wherein the pre-discharge device is an N-channel metal-oxide semiconductor (NMOS) transistor.

20 . The memory device of claim 18 , wherein the read merge circuitry further comprises:
a first equalizing device coupled to the node of the first LBL; and a second equalizing device coupled to the node of the second LBL, wherein the first equalizing device and the second equalizing device are further coupled to each other to form the equalization path.

21 . The memory device of claim 20 , wherein the first equalizing device comprises a N-channel metal-oxide semiconductor (NMOS) transistor, and wherein a gate of the NMOS transistor is

Assignees

• Intel Corp

Inventors

• Ghosh Amlan
• Merchant Feroze
• Kulkarni Jaydeep
• Riley John R

Classifications

• G11C7/12

  Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines · CPC title

• G11C8/16 Primary

  Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups · CPC title

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title