Phase difference control circuit

Patent metadata

Field	Value
Publication number	US-2024113854-A1
Application number	US-202318111889-A
Country	US
Kind code	A1
Filing date	Feb 21, 2023
Priority date	Sep 30, 2022
Publication date	Apr 4, 2024
Grant date	—

Abstract

Internal phase shifting is achieved by adding a feedback divider to a feedback loop of a phase locked loop circuit configured to determine a transmission frequency of a wireless transmission terminal and adding a phase adjustment current to a loop current. Since the phase adjustment current is applied to an adder circuit, a phase difference is maintained even when the feedback loop is in a stable state, and accordingly, an output of the feedback divider maintains the phase difference with a reference frequency as intended by the phase adjustment current applied to the adder circuit.

First claim

What is claimed is:

1 . A phase shift circuit comprising:
a phase locked loop circuit including a feedback divider in a feedback loop; and an adder circuit configured to add a phase adjustment current to a loop current of the phase locked loop circuit.

2 . The phase shift circuit of claim 1 , wherein the phase locked loop circuit further includes:
a first phase frequency detector (PFD) configured to compare a phase between a reference clock and an input frequency to output a first comparison signal; a first charge pump configured to perform charging and discharging according to the first comparison signal to output a loop current; a loop filter configured to filter the loop current; and a voltage-controlled oscillator configured to oscillate according to a loop filter output voltage, wherein the feedback divider is configured to divide an output frequency of the voltage-controlled oscillator to supply the divided output frequency as an input frequency to the first PFD.

3 . The phase shift circuit of claim 1 , further comprising an adjustment current generation unit configured to output a phase adjustment current signal from a control word output from a controller.

4 . The phase shift circuit of claim 3 , wherein the adjustment current generation unit is a digital-to-analog converter configured to convert the control word output from the controller to an analog signal and output the analog signal as the phase adjustment current signal.

5 . The phase shift circuit of claim 2 , further comprising an adjustment current generation unit configured to generate a phase adjustment current signal and output the phase adjustment current signal to the adder circuit.

6 . The phase shift circuit of claim 5 , wherein the adjustment current generation unit includes:
a divider configured to receive an output of the feedback divider and synchronize the output with an output of the voltage-controlled oscillator to output the synchronized output; a second phase frequency detector (PFD) configured to compare a phase between the reference clock and the output of the divider to output a second comparison signal; and a second charge pump configured to perform charging and discharging according to the second comparison signal to output a phase adjustment current.

7 . The phase shift circuit of claim 6 , further comprising:
a first random charge/discharge switching unit configured to connect a plurality of first current sources and one arbitrarily selected among the plurality of first current sources according to the first comparison signal to a charge/discharge input of the first charge pump; and a second random charge/discharge switching unit configured to connect a plurality of second current sources and one arbitrarily selected among the plurality of second current sources according to the second comparison signal to a charge/discharge input of the second charge pump.

8 . The phase shift circuit of claim 6 , further comprising a delay locked loop configured to delay the output of the voltage-controlled oscillator to supply the output as a synchronization input of the divider.

9 . The phase shift circuit of claim 8 , wherein the delay locked loop is a digital delay locked loop configured to delay the output of the voltage-controlled oscillator according to a delay control word to supply the output as the synchronization input of the divider.

10 . The phase shift circuit of claim 7 , further comprising a digital-to-analog converter configured to convert a control word output from a controller to an analog signal, and supply the analog signal as an additional phase adjustment signal to the adder circuit.

11 . The phase shift circuit of claim 5 , wherein the adjustment current generation unit includes:
a flip-flop configured to receive an output of the feedback divider and synchronize the output with an output of the voltage-controlled oscillator to output the synchronized output; a second phase frequency detector (PFD) configured to compare a phase between the reference clock and the output of the flip-flop to output a second comparison signal; and a second charge pump configured to perform charging and discharging according to the second comparison signal to output a loop current.

12 . The phase shift circuit of claim 11 , further comprising a digital-to-analog converter configured to convert a control word output from a controller to an analog signal, and supply the analog signal as an additional phase adjustment current signal to the adder circuit.

13 . A wireless transmission device comprising:
the phase shift circuit according to claim 1 ; a modulator configured to modulate input data with a signal phase shifted in the phase shift circuit; a power amplifier configured to amplify an output of the modulator; and an antenna configured to wirelessly transmit an output of the power amplifier.

Assignees

• Skaichips Co Ltd
• Research & Business Found Sungkyunkwan Univ

Inventors

• Lee Kang Yoon
• Huh Hyung Ki
• Jo Jong Wan
• Kim Ho Won

Classifications

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03L7/097

  using a comparator for comparing the voltages obtained from two frequency to voltage converters · CPC title

• H03L7/0895

  Details of the current generators (H03L7/0893 takes precedence) · CPC title

• H03L7/087 Primary

  using at least two phase detectors or a frequency and phase detector in the loop · CPC title