Vertical Transistor Cell Structures Utilizing Topside and Backside Resources

Patent metadata

Field	Value
Publication number	US-2024105727-A1
Application number	US-202318448746-A
Country	US
Kind code	A1
Filing date	Aug 11, 2023
Priority date	Sep 23, 2022
Publication date	Mar 28, 2024
Grant date	—

Abstract

Various structures that implement topside metal routing and backside metal routing in combination with vertical transistors are disclosed. The various structures include cells that form inverter devices, NAND devices, and MUX (multiplexer) devices. The disclosed cells include two or four vertical transistors with various connections made to the transistors that include either connected gate logic for inverter and NAND devices or disconnected gate logic for MUX devices.

First claim

What is claimed is:

1 . An apparatus, comprising:
a first vertical transistor formed in a transistor region of an integrated circuit cell structure, the first vertical transistor having a lower source/drain region, a first gate, and an upper source/drain region stacked in a vertical dimension; a second vertical transistor formed in the transistor region, the second vertical transistor having a lower source/drain region, a second gate, and an upper source/drain region stacked in the vertical dimension, wherein the second vertical transistor is parallel to the first vertical transistor along a first direction in a horizontal dimension with at least some spacing in the first direction between the vertical transistors; a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes parallel signal routing in the first direction; at least one gate via coupled between the signal routing in the first metal layer and at least one of the first gate and the second gate; and a second metal layer located below the transistor region in the vertical dimension, wherein the second metal layer includes parallel power routing in a second direction perpendicular to the first direction in the horizontal dimension.

2 . The apparatus of claim 1 , wherein the first vertical transistor and the second vertical transistor are complementary transistor types.

3 . The apparatus of claim 1 , wherein the first vertical transistor is a PMOS transistor, and wherein the second vertical transistor is an NMOS transistor.

4 . The apparatus of claim 1 , further comprising a gate bridge that extends across the at least some spacing in the first direction between the vertical transistors, wherein the gate bridge is coupled between the first gate and the second gate.

5 . The apparatus of claim 4 , wherein the at least one gate via is coupled between the signal routing in the first metal layer and a portion of the gate bridge in the at least some spacing between the vertical transistors.

6 . The apparatus of claim 5 , wherein the at least one gate via is coupled between the gate bridge and a signal input route of the signal routing in the first metal layer.

7 . The apparatus of claim 1 , further comprising a third metal layer positioned below the lower source/drain regions and above the second metal layer, wherein the third metal layer includes at least one metal portion in contact with at least one of the lower source/drain regions.

8 . The apparatus of claim 7 , further comprising a lower via coupled between the at least one metal portion in the third metal layer and the power routing in the second metal layer.

9 . The apparatus of claim 4 , further comprising:
a fourth metal layer positioned above the upper source/drain regions and below the first metal layer, wherein the fourth metal layer includes at least one metal portion in contact with at least one of the upper source/drain regions.

10 . The apparatus of claim 9 , wherein the fourth metal layer includes:
a first contact coupled to the upper source/drain region of the first transistor, the first contact having a portion extending away from the upper source/drain region in the second direction; and a second contact coupled to the upper source/drain region of the second transistor, the second contact having a portion extending away from the upper source/drain region in the second direction.

11 . The apparatus of claim 10 , further comprising:
a first contact via coupled between an end of the first contact distal from the upper source/drain region of the first transistor and a signal output route of the signal routing in the first metal layer; and a second contact via coupled between an end of the second contact distal from the upper source/drain region of the second transistor and the signal output route.

12 . The apparatus of claim 9 , further comprising:
a third vertical transistor formed in the transistor region, the third vertical transistor having a lower source/drain region, a third gate, and an upper source/drain region stacked in the vertical dimension, wherein the third vertical transistor is parallel to the first vertical transistor along the second direction; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source/drain region, a fourth gate, and an upper source/drain region stacked in the vertical dimension, wherein the fourth vertical transistor is parallel to the third vertical transistor along the first direction in the horizontal dimension with at least some spacing in the first direction between the third and fourth vertical transistors; a first contact in the fourth metal layer, wherein the first contact is coupled between the upper source/drain region of the first transistor and the upper source/drain region of the third transistor, the first contact having a portion extending beyond the upper source/drain region of the third transistor in the second direction; and a second contact in the fourth metal layer, wherein the second contact is coupled between the upper source/drain region of the second transistor and the upper source/drain region of the fourth transistor.

13 . The apparatus of claim 12 , further comprising:
a first contact via coupled between the portion of the first contact extending beyond the upper source/drain region of the third transistor in the second direction and a signal output route of the signal routing in the first metal layer; a metal extension portion coupled to a bottom of the lower source/drain region of the fourth transistor, wherein the metal extension portion extends towards a boundary of the integrated circuit cell from the bottom of the lower source/drain region in the second direction; and a second contact via coupled between the metal extension portion and the signal output route.

14 . The apparatus of claim 9 , wherein the fourth metal layer includes:
a first contact coupled between the upper source/drain region of the first transistor and the upper source/drain region of the second transistor.

15 . The apparatus of claim 14 , further comprising:
a third vertical transistor formed in the transistor region, the third vertical transistor having a lower source/drain region, a third gate, and an upper source/drain region stacked in the vertical dimension, wherein the third vertical transistor is parallel to the first vertical transistor along the second direction; a fourth vertical transistor formed in the transistor region, the fourth vertical transistor having a lower source/drain region, a fourth gate, and an upper source/drain region stacked in the vertical dimension, wherein the fourth vertical transistor is parallel to the third vertical transistor along the first direction in the horizontal dimension with at least some spacing in the first direction between the third and fourth vertical transistors; and a second contact in the fourth metal layer, wherein the second contact is coupled between the upper source/drain region of the third transistor and the upper source/drain region of the fourth transistor.

16 . The apparatus of claim 15 , further comprising a third contact coupled between the lower source/drain regions of the first, second, third, and fourth vertical transistors, wherein the first gate, the second gate, the third gate, and the fourth gate include, respectively, a first gate extension, a second gate extension, a third gate extension, and a fourth gate extension, wherein each gate extension extends horizontally at least some distance in the second

Assignees

• Apple Inc

Inventors

• Miao Xin
• Raghavan Praveen
• Hoffmann Thomas
• Sinha Saurabh P

Classifications

• H10D84/837

  comprising vertical IGFETs · CPC title

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10D84/907 Primary

  CMOS gate arrays · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title