Gate cuts in a grating pattern across an integrated circuit

Patent metadata

Field	Value
Publication number	US-2024088218-A1
Application number	US-202217943443-A
Country	US
Kind code	A1
Filing date	Sep 13, 2022
Priority date	Sep 13, 2022
Publication date	Mar 14, 2024
Grant date	—

Abstract

Techniques are provided herein to form an integrated circuit having a grating pattern of gate cut structures such that a gate cut structure extends between the gate layers of adjacent semiconductor devices and between the source or drain regions (e.g., epitaxial regions) of the adjacent semiconductor devices. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. In some such examples, a gate cut structure is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate electrode of one semiconductor device from the gate electrode of the other semiconductor device. The gate cut structure further extends to separate the source or drain regions of the neighboring semiconductor devices. Subsequent processes allow neighboring gate or source or drain regions connections.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first semiconductor body extending lengthwise in a first direction between a first source region and a first drain region; a second semiconductor body extending lengthwise in the first direction between a second source region and a second drain region; a gate structure extending in a second direction different from the first direction, the gate structure including a first gate layer across the first semiconductor body and a second gate layer across the second semiconductor body; and a dielectric wall extending in the first direction between the first and second source regions, the first and second drain regions, and the first and second gate layers.

2 . The integrated circuit of claim 1 , wherein the dielectric wall comprises silicon and nitrogen, or silicon and oxygen.

3 . The integrated circuit of claim 1 , wherein the dielectric wall extends in the first direction between additional adjacent source or drain regions of additional semiconductor devices.

4 . The integrated circuit of claim 1 , further comprising a conductive layer over a top surface of the dielectric wall, such that the conductive layer contacts the first gate layer on a first side of the dielectric wall and contacts the second gate layer on an opposite second side of the dielectric wall.

5 . The integrated circuit of claim 1 , further comprising spacer structures on sidewalls of each of the first and second gate layers, wherein a dielectric material of the spacer structures is a same dielectric material as the dielectric wall.

6 . The integrated circuit of claim 1 , wherein the dielectric wall is a first dielectric wall, and there is substantially equal spacing in the second direction between the first dielectric wall and a second dielectric wall to a first side of the first dielectric wall, and in the second direction between the first dielectric wall and a third dielectric wall to a second side of the first dielectric wall.

7 . A printed circuit board comprising the integrated circuit of claim 1 .

8 . A method of forming an integrated circuit, comprising:
forming a plurality of fins comprising semiconductor material extending above a top surface of a dielectric layer, the plurality of fins each extending lengthwise in a first direction; forming source or drain regions at opposite ends of the semiconductor material of each of the plurality of fins in the first direction; forming a dielectric fill between adjacent source or drain regions; forming strips of gate layers over the semiconductor material of the plurality of fins, the strips of gate layers extending lengthwise in a second direction different from the first direction; etching trenches at least through the strips of gate layers and through the dielectric fill, the trenches extending lengthwise in the second direction; and filling the trenches with a dielectric material.

9 . The method of claim 8 , wherein etching trenches comprises forming a trench through each strip of gate layers between adjacent pairs of fins using a single etching process.

10 . The method of claim 8 , wherein the semiconductor material comprises first semiconductor layers alternating with second semiconductor layers and the method further comprises removing the second semiconductor layers to form nanoribbons from the first semiconductor layers extending lengthwise in the first direction.

11 . The method of claim 8 , further comprising:
forming a dielectric cap layer over the strips of gate layers; forming one or more conductive contacts over corresponding one or more source or drain regions; forming one or more plugs over corresponding one or more other source or drain regions; assembling a first polymer material on the dielectric cap layer; and assembling a second polymer material on the one or more conductive contacts and the one or more plugs.

12 . The method of claim 11 , wherein the second polymer material extends across the trenches with the dielectric material.

13 . The method of claim 11 , further comprising:
replacing the first polymer material with a dielectric masking material; lithographically patterning the dielectric masking material to from openings above the dielectric cap layer; removing the exposed dielectric cap layer within the openings; and forming conductive bridges within the openings.

14 . An integrated circuit comprising:
a first semiconductor body extending in a first direction from a first side of a first source or drain region; a second semiconductor body extending in the first direction from a second side of the first source or drain region; a third semiconductor body extending in the first direction from a first side of a second source or drain region; a fourth semiconductor body extending in the first direction from a second side of the second source or drain region; a first gate structure extending across the first semiconductor body in a second direction different from the first direction; a second gate structure extending across the second semiconductor body in the second direction; a third gate structure extending across the third semiconductor body in the second direction; a fourth gate structure extending across the fourth semiconductor body in the second direction; and a dielectric wall extending in the first direction between the first gate structure and the third gate structure, between the first source or drain region and the second source or drain region, and between the second gate structure and the fourth gate structure.

15 . The integrated circuit of claim 14 , wherein the first gate structure extends colinear with the third gate structure in the second direction, and the second gate structure extends colinear with the fourth gate structure in the second direction.

16 . The integrated circuit of claim 14 , further comprising a gate dielectric layer around the first, second, third, and fourth semiconductor bodies.

17 . The integrated circuit of claim 16 , wherein the gate dielectric layer is not present on sidewalls of the dielectric wall as it extends between the first gate structure and the third gate structure and between the second gate structure and the fourth gate structure.

18 . The integrated circuit of claim 14 , further comprising a conductive layer over a top surface of the dielectric wall between the first gate structure and the third gate structure, such that the conductive layer contacts both a gate layer of the first gate structure and a gate layer of the second gate structure.

19 . The integrated circuit of claim 18 , further comprising sidewall spacers along sidewalls of the first gate structure and the third gate structure, wherein the conductive layer is aligned between the sidewall spacers.

20 . A printed circuit board comprising the integrated circuit of claim 14 .

Assignees

• Intel Corp

Inventors

• Koh Shao-Ming
• Guler Leonard P
• Singh Gurpreet
• Chandhok Manish
• Prince Matthew J

Classifications

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0128

  Manufacturing their channels · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/013

  Manufacturing their source or drain regions, e.g. silicided source or drain regions · CPC title

• H10D62/151

  of IGFETs  (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713) · CPC title