Self-aligned metal gate for multigate device and method of forming thereof

Patent metadata

Field	Value
Publication number	US-2022013410-A1
Application number	US-202117224334-A
Country	US
Kind code	A1
Filing date	Apr 7, 2021
Priority date	Jul 13, 2020
Publication date	Jan 13, 2022
Grant date	—

Abstract

Devices and methods that a first gate structure wrapping around a channel layer disposed over the substrate, a second gate structure wrapping around another channel layer disposed over the substrate and a dielectric fin structure formed over a shallow trench isolation (STI) feature and between the first and second gate structures. At least one metallization layer is formed on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extends from the first gate structure to the second gate structure.

First claim

What is claimed is:

1 . A device comprising:
a substrate; a first gate structure wrapping around a channel layer disposed over the substrate; a second gate structure wrapping around another channel layer disposed over the substrate; a dielectric fin structure formed over a shallow trench isolation (STI) feature, wherein the dielectric fin structure is between the first gate structure and the second gate structure; at least one metallization layer on the first gate structure, the dielectric fin structure, and the second gate structure and contiguously extending from the first gate structure to the second gate structure.

2 . The device of claim 1 , wherein the at least one metallization layer includes a seed layer and a first metal layer.

3 . The device of claim 2 , wherein the seed layer includes at least one of titanium (Ti), titanium nitride (TiN), tantalum (TaN), or tungsten (W).

4 . The device of claim 3 , wherein a sidewall of the seed layer interfaces the dielectric fin structure.

5 . The device of claim 1 , wherein the at least one metallization layer physically interfaces a top surface of the dielectric fin structure.

6 . The device of claim 5 , wherein the top surface of the dielectric fin structure is a high-k dielectric material.

7 . The device of claim 1 , further comprising:
a third gate structure separated from the second gate structure by a second dielectric fin, wherein a gate separation feature is disposed over the second dielectric fin.

8 . The device of claim 7 , wherein the at least one metallization layer abuts a sidewall of the gate separation feature.

9 . The device of claim 8 , wherein an end of the at least metallization layer abuts the sidewall of the gate separation feature includes a curvilinear surface.

10 . A device, comprising:
a first channel layer disposed between first source/drain features over a substrate; a first metal gate that surrounds the first channel layer; a second channel layer disposed between second source/drain features over the substrate; a second metal gate that surrounds the second channel layer; a dielectric fin disposed between and separating the first metal gate and the second metal gate; a first portion of a conductive layer over the first metal gate; a second portion of the conductive layer over the second metal gate; and an isolation layer between the first portion and second portion of the conductive layer and over the dielectric fin, wherein at least one of the first portion of the conductive layer or the second portion of the conductive layer includes a rounded terminal end abutting the isolation layer.

11 . The device of claim 10 , wherein the isolation layer interfaces a top surface of the dielectric fin.

12 . The device of claim 10 , further comprising: an etch stop layer between the first portion of the conductive layer and the first metal gate.

13 . The device of claim 10 , wherein a seed layer interposes the first portion of the conductive layer and the first metal gate.

14 . The device of claim 13 , wherein a top surface of the seed layer is below a top surface of the dielectric fin.

15 . A method including,
forming a first gate structure, a first source structure and a first drain structure of a first gate all around (GAA) device over a substrate; forming a second gate structure, a second source structure and a second drain structure of a second GAA over the substrate, wherein a dielectric fin is disposed between the first gate structure and the second gate structure; depositing a dummy layer over the first gate structure, the second gate structure, and the dielectric fin; patterning the dummy layer to form a trench within the dummy layer over the dielectric fin; filling the trench with a dielectric material to form a dielectric feature; removing the patterned dummy layer after filling the trench; and depositing at least one conductive layer having a first portion over the first gate structure and a second portion of the second gate structure, wherein the dielectric feature interposes the first and second portion.

16 . The method of claim 15 , further comprising:
depositing insulating material over the first and second portions of the conductive layer.

17 . The method of claim 15 , further comprising:
forming a conductive via to the second portion of the conductive layer.

18 . The method of claim 15 , wherein the patterning the dummy layer to form the trench includes selectively etching material of the dummy layer while substantially not etching the first gate structure or the second gate structure.

19 . The method of claim 15 , wherein the depositing the at least one conductive layer includes depositing a seed layer and an overlying metal layer.

20 . The method of claim 15 wherein the depositing the at least one conductive layer includes depositing conductive material of the at least one conductive layer having a rounded terminal region abutting the dielectric feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• You Jia-Chuan
• Pan Kuan-Ting
• Ju Shi Ning
• Chiang Kuo-Cheng
• Wang Chih-Hao

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10W20/4441

  the principal metal being a refractory metal · CPC title

• H10W20/0698

  Local interconnections · CPC title

• H10W20/083

  the openings being via holes penetrating underlying conductors · CPC title

• H10W20/042

  the barrier, adhesion or liner layers being seed or nucleation layers · CPC title