Semiconductor package structure and fabrication method thereof

Patent metadata

Field	Value
Publication number	US-2024079288-A1
Application number	US-202318506742-A
Country	US
Kind code	A1
Filing date	Nov 10, 2023
Priority date	Aug 31, 2015
Publication date	Mar 7, 2024
Grant date	—

Abstract

A method of fabricating a semiconductor package structure is provided. The structure is configured to include a base substrate, a die placed on the base substrate, the die including a semiconductor device, a solder bump placed on one surface of the die to exhaust heat generated in the die to an outside; and a solder ball placed on other surface of the die facing the one surface to transmit a signal, which is produced by the semiconductor device of the die, to an external device.

First claim

1 . A semiconductor package structure, comprising:
a first package structure comprising:
a first redistribution structure comprising metallization patterns and dielectric layers;
a first die over and electrically connected to the first redistribution structure, an active side of the first die comprising contact pads facing the first redistribution structure, and an inactive side of the first die comprising a joining pattern and a solder bump joined to the joining pattern on the first die;
a second die over the first die;
a first connecting plug adjacent the first die and the second die, the first connecting plug electrically connected to the first redistribution structure;
an encapsulant laterally encapsulating the first die, the second die, and the first connecting plug; and
thermal elements on a back-side of the second die;
a second redistribution structure over the back side of the second die and the first connecting plug, the second redistribution structure comprising metallization patterns and a dielectric layer, the second redistribution structure being electrically connected to the first connecting plug; and a second package structure bonded to the metallization patterns of the second redistribution structure with a first set of conductive connectors.

2 . The semiconductor package structure of claim 1 , further comprising:
a base substrate interposed between the first die and the first connecting plug, collectively, and the second die, the base substrate including heat dissipation plugs penetrating the base substrate; and a solder mask disposed on the base substrate, the solder mask defining an opening area that corresponds to at least two of the heat dissipation plugs.

3 . The semiconductor package structure of claim 2 , wherein the solder bump connects the heat dissipation plugs and the joining pattern to each other.

4 . The semiconductor package structure of claim 3 , wherein the solder bump is disposed in the opening area between the heat dissipation plugs and the first die, and is configured to discharge heat generated in the first die to an outside.

5 . The semiconductor package structure of claim 3 , wherein the joining pattern is electrically disconnected from the first die.

6 . The semiconductor package structure of claim 3 , wherein the solder bump comprises a first portion facing the first die and a second portion facing the heat dissipation plugs, and
wherein a width of the first portion is different than a width of the second portion.

7 . The semiconductor package structure of claim 3 , wherein a direction of heat, which is generated in the first die and is discharged to the outside through the solder bump, and a direction of a signal, which is produced by a semiconductor device in the first die and is transmitted to an external device through the solder bump, are anti-parallel to each other.

8 . The semiconductor package structure of claim 3 , wherein the solder bump is connected to two of the heat dissipation plugs.

9 . The semiconductor package structure of claim 3 , wherein the joining pattern provides an interface between the first die and the solder bump, and
wherein the joining pattern is electrically disconnected from the first die.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Youngho
• Park Hwanpil

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title