Semiconductor device

Patent metadata

Field	Value
Publication number	US-2024074190-A1
Application number	US-202318117961-A
Country	US
Kind code	A1
Filing date	Mar 6, 2023
Priority date	Aug 30, 2022
Publication date	Feb 29, 2024
Grant date	—

Abstract

A semiconductor device includes a substrate, a source structure disposed on the substrate, and cell stack structures disposed on the source structure. The semiconductor device also includes a dummy stack structure disposed between the cell stack structures on the source structure and vertical barriers disposed between the dummy stack structure and the cell stack structures. The semiconductor device further includes at least one lower protective pattern disposed at a lower portion of the dummy stack structure between the vertical barriers.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a substrate; a source structure disposed on the substrate; cell stack structures disposed on the source structure; a dummy stack structure disposed between the cell stack structures on the source structure; vertical barriers disposed between the dummy stack structure and the cell stack structures; and at least one lower protective pattern disposed at a lower portion of the dummy stack structure between the vertical barriers.

2 . The semiconductor device of claim 1 , wherein the dummy stack structure includes a first stack structure and a second stack structure on the first stack structure, and
wherein the at least one lower protective pattern is disposed at the same level as the first stack structure.

3 . The semiconductor device of claim 1 , further comprising:
an opening penetrating the source structure; a source insulating layer disposed in the opening; and a peripheral contact plug comprising an upper portion penetrating through the dummy stack structure disposed on the top of the source insulating layer.

4 . The semiconductor device of claim 3 , wherein the peripheral contact plug comprises a lower portion extending from the upper portion and penetrating through the source insulating layer disposed in the opening.

5 . The semiconductor device of claim 4 , further comprising a peripheral circuit structure disposed between the substrate and the source structure,
wherein the lower portion of the peripheral contact plug is connected to the peripheral circuit structure.

6 . The semiconductor device of claim 4 , wherein the lower portion of the peripheral contact plug is spaced apart from the source structure by the source insulating layer disposed in the opening.

7 . The semiconductor device of claim 3 , wherein the peripheral contact plug is disposed between two of the at least one lower protective pattern.

8 . The semiconductor device of claim 1 , wherein the dummy stack structure includes dummy interlayer insulating layers and sacrificial insulating layers, which are alternately stacked,
wherein the cell stack structures include interlayer insulating layers and conductive patterns, which are alternately stacked, and wherein the dummy stack structure is isolated from the cell stack structures by the vertical barriers.

9 . The semiconductor device of claim 8 , wherein the dummy stack structure includes a first stack structure and a second stack structure on the first stack structure,
wherein the first stack structure includes a lowermost sacrificial insulating layer of the dummy stack structure, and wherein the at least one lower protective pattern penetrates the lowermost sacrificial insulating layer of the dummy stack structure.

10 . The semiconductor device of claim 1 , further comprising a support penetrating through a cell stack structure of the cell stack structures to contact a top of the source structure.

11 . A semiconductor device comprising:
a contact structure; a source structure surrounding the contact structure; a first stack structure disposed on the top of the contact structure and the source structure; at least one lower protective pattern in contact with the source structure and penetrating the first stack structure; and a second stack structure disposed on the top of the lower protective pattern and the first stack structure.

12 . The semiconductor device of claim 11 , wherein the contact structure includes:
a source insulating layer; and a peripheral contact plug penetrating through the source insulating layer.

13 . The semiconductor device of claim 12 , further comprising a peripheral circuit structure disposed below the source structure,
wherein the peripheral contact plug is connected to the peripheral circuit structure.

14 . The semiconductor device of claim 12 , wherein the peripheral contact plug is spaced apart from the source structure by the source insulating layer.

15 . The semiconductor device of claim 12 , wherein the peripheral contact plug is disposed between two of the at least one lower protective pattern.

16 . The semiconductor device of claim 11 , further comprising a vertical barrier surrounding the first stack structure and the second stack structure,
wherein the first stack structure and the second stack structure include interlayer insulating layers and sacrificial insulating layers, which are alternately stacked.

17 . The semiconductor device of claim 16 , wherein the first stack structure includes a lowermost sacrificial insulating layer, and
wherein the at least one lower protective pattern penetrates the lowermost sacrificial insulating layer of the first stack structure.

18 . The semiconductor device of claim 11 , further comprising:
a cell stack structure spaced apart from the first stack structure and the second stack structure; and a support in contact with the top of the source structure and penetrating the cell stack structure.

Assignees

• Sk Hynix Inc

Inventors

• Kim Jae Taek

Classifications

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10

  characterised by the top-view layout · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title