Sharing register file usage between fused processing resources

Patent metadata

Field	Value
Publication number	US-2024053985-A1
Application number	US-202318485089-A
Country	US
Kind code	A1
Filing date	Oct 11, 2023
Priority date	Sep 25, 2019
Publication date	Feb 15, 2024
Grant date	—

Abstract

Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.

First claim

1 .- 20 . (canceled)

21 . An apparatus comprising:
a processor having processing resources and coupled to a memory, the processor to: generate, by a first processing resource, a first output representing a matrix multiplication of a first portion of a first set of matrix data and a second set of matrix data; and generate, by a second processing resource, a second output representing a matrix multiplication of the second portion of the first set of matrix data and the second set of matrix data.

22 . The apparatus of claim 21 , wherein the processor is further to facilitate storage of the first output and the second output in a set of registers, and wherein the first processing resource and the second processing resource are fused.

23 . The apparatus of claim 21 , wherein the processor is further to:
receive an instruction to initiate a matrix multiplication operation; and cause the first memory arbiter circuitry to write, into a first set of registers, a first set of matrix data from a shared local memory communicatively coupled to the first processing resource by a first data bus and the second processing resource by a second data bus.

24 . The apparatus of claim 23 , wherein the processor is further to:
share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation; and allocate a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

25 . The apparatus of claim 23 , wherein the processor is further to:
write a second set of matrix data into a second set of registers; and generate a signal to execute the matrix multiplication operation using the first processing resource and the second processing resource.

26 . A method comprising:
generating, by a first processing resource associated with a processor of a computing device, a first output representing a matrix multiplication of a first portion of a first set of matrix data and a second set of matrix data; and generating, by a second processing resource associated with a second processor of a computing device, a second output representing a matrix multiplication of the second portion of the first set of matrix data and the second set of matrix data.

27 . The method of claim 26 , further comprising storing the first output and the second output in a set of registers, and wherein the first processing resource and the second processing resource are fused.

28 . The method of claim 26 , further comprising:
receiving an instruction to initiate a matrix multiplication operation; and causing the first memory arbiter circuitry to write, into a first set of registers, a first set of matrix data from a shared local memory communicatively coupled to the first processing resource by a first data bus and the second processing resource by a second data bus.

29 . The method of claim 28 , further comprising:
sharing the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation; and allocating a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

30 . The method of claim 23 , further comprising:
writing a second set of matrix data into a second set of registers; and generating a signal to execute the matrix multiplication operation using the first processing resource and the second processing resource.

31 . At least one computer-readable medium having stored thereon instructions which, when executed, cause a computing device to perform operations comprising:
generating, by a first processing resource, a first output representing a matrix multiplication of a first portion of a first set of matrix data and a second set of matrix data; and generating, by a second processing resource, a second output representing a matrix multiplication of the second portion of the first set of matrix data and the second set of matrix data.

32 . The computer-readable medium of claim 31 , wherein the operations further comprise storing the first output and the second output in a set of registers, and wherein the first processing resource and the second processing resource are fused.

33 . The computer-readable medium of claim 31 , wherein the operations further comprise:
receiving an instruction to initiate a matrix multiplication operation; and causing the first memory arbiter circuitry to write, into a first set of registers, a first set of matrix data from a shared local memory communicatively coupled to the first processing resource by a first data bus and the second processing resource by a second data bus.

34 . The computer-readable medium of claim 33 , wherein the operations further comprise:
sharing the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation; and allocating a first portion of the first set of matrix data to the first processing resource and a second portion of the first set of matrix data to the second processing resource.

35 . The computer-readable medium of claim 33 , wherein the operations further comprise:
writing a second set of matrix data into a second set of registers; and generating a signal to execute the matrix multiplication operation using the first processing resource and the second processing resource.

Assignees

• Intel Corp

Inventors

• Maiyuran Subramaniam
• George Varghese
• Ray Joydeep
• Garg Ashutosh
• Parra Jorge
• Shah Shubh
• Marwaha Shubra

Classifications

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3001 Primary

  Arithmetic instructions · CPC title

• G06F9/5011

  the resources being hardware resources other than CPUs, Servers and Terminals · CPC title

• G06F17/16 Primary

  Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} · CPC title

• G06F9/3013

  according to data content, e.g. floating-point registers, address registers · CPC title