Power semiconductor device having counter-doped regions in both an active cell region and an inactive cell region

Patent metadata

Field	Value
Publication number	US-2024047517-A1
Application number	US-202217882064-A
Country	US
Kind code	A1
Filing date	Aug 5, 2022
Priority date	Aug 5, 2022
Publication date	Feb 8, 2024
Grant date	—

Abstract

A power semiconductor device includes: trench gate structures in an active cell region of a semiconductor substrate and extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings. Methods of producing the power semiconductor device are also described.

First claim

What is claimed is:

1 . A method of producing a power semiconductor device, the method comprising:
forming a plurality of trench gate structures in an active cell region of a semiconductor substrate, the plurality of trench gate structures extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; covering the plurality of trench gate structures with an electrically insulating material; forming, using a common mask, first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region and second contact openings vertically aligned with the trench gate structures in the inactive cell region; and implanting, using a common implantation process, a dopant species into the semiconductor substrate through the first contact openings and the second contact openings to form first counter-doped regions between the adjacent trench gate structures in the active cell region and second counter-doped regions underneath the trench gate structures in the inactive cell region.

2 . The method of claim 1 , further comprising:
after the common implantation process, forming first contacts in the first contact openings and second contacts in the second contact openings, wherein the first contacts and the second contacts are at different potentials.

3 . The method of claim 2 , further comprising:
forming a patterned power metallization layer above the electrically insulating material such that a first part of the patterned power metallization layer contacts the first contacts and a second part of the patterned power metallization layer partly contacts the second contacts; and forming a passivation on any part of the first contacts and the second contacts not covered by the patterned power metallization layer.

4 . The method of claim 1 , wherein forming the first contact openings and the second contact openings comprises:
etching into the semiconductor substrate between the adjacent trench gate structures in the active cell region and into a gate electrode material of the trench gate structures in the inactive cell region.

5 . The method of claim 1 , wherein in the inactive cell region, the plurality of trench gate structures intersect a trench gate bus structure that electrically interconnects a gate electrode material of the trench gate structures.

6 . The method of claim 5 , further comprising:
forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region; and implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region.

7 . The method of claim 1 , wherein the first counter-doped regions and the second counter-doped regions merge with one another along a border region between the active cell region and the inactive cell region.

8 . The method of claim 1 , wherein the dopant species is implanted into the semiconductor substrate through the first contact openings and the second contact openings at an angle relative to a first main surface of the semiconductor substrate.

9 . The method of claim 1 , further comprising:
forming a trench shielding structure in the inactive cell region and that laterally surrounds the plurality of trench gate structures, wherein the trench shielding structure is electrically floating; forming, using the common mask, a third contact opening vertically aligned with the trench shielding structure in the inactive cell region; and implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench shielding structure in the inactive cell region.

10 . The method of claim 1 , further comprising:
forming a trench gate bus structure in the inactive cell region; forming, using the common mask, a third contact opening vertically aligned with the trench gate bus structure in the inactive cell region; implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench gate bus structure in the inactive cell region; and electrically connecting a metal line in the trench gate bus structure to gate electrodes in the plurality of trench gate structures.

11 . The method of claim 1 , further comprising:
forming a trench structure in the inactive cell region; forming, using the common mask, a third contact opening vertically aligned with the trench structure in the inactive cell region; and implanting, using the common implantation process, the dopant species into the semiconductor substrate through the third contact opening to counter-dope the semiconductor substrate underneath the trench structure in the inactive cell region, wherein the counter-doped semiconductor substrate underneath the trench structure in the inactive cell region is electrically floating.

12 . A power semiconductor device, comprising:
a plurality of trench gate structures in an active cell region of a semiconductor substrate, the plurality of trench gate structures extending into an inactive cell region of the semiconductor substrate that adjoins the active cell region; an electrically insulating material covering the plurality of trench gate structures; first contact openings in the electrically insulating material between adjacent trench gate structures in the active cell region; second contact openings in the electrically insulating material vertically aligned with the trench gate structures in the inactive cell region; first counter-doped regions between the adjacent trench gate structures in the active cell region and vertically aligned with the first contact openings; second counter-doped regions underneath the trench gate structures in the inactive cell region and vertically aligned with the second contact openings; first contacts in the first contact openings; and second contacts in the second contact openings.

13 . The power semiconductor device of claim 12 , wherein the first contacts and the second contacts are aligned with one another in a lengthwise extension of the first contacts and the second contacts.

14 . The power semiconductor device of claim 12 , wherein the first contacts and the second contacts are offset from one another in a lengthwise extension of the first contacts and the second contacts.

15 . The power semiconductor device of claim 12 , further comprising:
a patterned power metallization layer above the electrically insulating material and comprising a first part that contacts the first contacts and a second part that contacts the second contacts; and a passivation covering any part of the first contacts and the second contacts not covered by the patterned power metallization layer.

16 . The power semiconductor device of claim 12 , wherein the first contact openings are etched into the semiconductor substrate between the adjacent trench gate structures in the active cell region, and wherein the second contact openings are etched into a gate electrode material of the trench gate structures in the inactive cell region.

17 . The power semiconductor device of claim 12 , wherein in the inactive cell region, the plurality of trench gate structures intersect a trench gate bus structure that

Assignees

• Infineon Technologies Austria Ag

Inventors

• Haase Robert
• Amali Adam
• Henson Timothy
• Ma Ling
• Malani Kishore Lakhmichand

Classifications

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10D62/111 Primary

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title