Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-2023411512-A1
Application number	US-202318189541-A
Country	US
Kind code	A1
Filing date	Mar 24, 2023
Priority date	May 31, 2022
Publication date	Dec 21, 2023
Grant date	—

Abstract

An improved structure and a manufacturing method of a vertical type power MOSFET having a super junction configuration is disclosed. The improved structure and the manufacturing method of the vertical type power MOSFET comprising: a step of preparing a semiconductor substrate SB including an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL; a step of forming a trench GT in the p-type epitaxial layer EP by using an etching mask with a predetermined opening width; and a step of introducing an n-type impurity into a bottom portion of the trench GT using the etching mask with the predetermined opening width, whereby forming an n-type column NC at the bottom of trench GT and reaching the semiconductor layer SL.

First claim

What is claimed is:

1 . A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing a semiconductor substrate having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type; (b) forming a gate trench having a predetermined width and reaching an intermediate depth from an upper surface of the second semiconductor layer by using an etching mask having a predetermined opening width; (c) forming a first column of the first conductivity type in the second semiconductor layer by introducing an impurity of the first conductivity type into a bottom of the gate trench such that the first column reaches the first semiconductor layer; and (d) forming a body region of the second conductivity type and a source region of the first conductivity type in the second semiconductor layer at a side surface of the gate trench; wherein the introduction of the impurity of the first conductivity type in the step (c) is performed by an ion implantation using the etching mask in the step (b) defining an opening of the gate trench.

2 . A method of manufacturing a semiconductor device according to claim 1 , wherein the first column is in contact with the bottom surface of the gate trench.

3 . A method of manufacturing a semiconductor device according to claim 1 , wherein in the step (b), the step of the gate trench includes a step of forming a plurality of gate trenches in the second semiconductor layer, and
wherein a portion of the second semiconductor layer is formed between opposing side surfaces of two adjacent gate trenches.

4 . A method of manufacturing a semiconductor device according to claim 1 , wherein the first column is spaced from a bottom surface of the gate trench.

5 . A method of manufacturing a semiconductor device comprising the steps of:
(a) preparing a semiconductor substrate having a first semiconductor layer of a first conductivity type and a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; (b) forming a gate trench having a predetermined width and reaching an intermediate depth from an upper surface of the second semiconductor layer by using an etching mask having a predetermined opening width; (c) forming a first column of the first conductivity type in the second semiconductor layer by introducing an impurity of the first conductivity type into a bottom of the gate trench such that the first column reaches the first semiconductor layer; (d) forming a body region of a second conductivity type and a source region of the first conductivity type in the second semiconductor layer at a side surface of the gate trench, the second conductivity type being different from the first conductivity type; and (e) forming a second column of the first conductivity type in the second semiconductor layer by introducing an impurity of the second conductivity type into the second semiconductor layer such that the second column is spaced from the gate trench and is adjacent to the first column in a first direction along an upper surface of the second semiconductor layer; wherein the introduction of the impurity of the first conductivity type in the step (c) is performed by an ion implantation using the etching mask in the step (b) defining an opening of the gate trench.

6 . A method of manufacturing a semiconductor device according to claim 5 , wherein the first column is in contact with the bottom surface of the gate trench.

7 . A method of manufacturing a semiconductor device according to claim 5 , wherein the first column is spaced from a bottom surface of the gate trench.

8 . A semiconductor device comprising:
a semiconductor substrate having a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type formed on the first semiconductor layer, the second conductivity type being different from the first conductivity type; a gate trench having a predetermined width and reaching an intermediate depth from an upper surface of the second semiconductor layer; a gate electrode formed in the gate trench via an insulating film; a first column of the first conductivity type formed in the second semiconductor layer under a bottom surface of the gate trench and reaching the first semiconductor layer; and a body region of the second conductivity type and a source region of the first conductivity type formed in the second semiconductor layer on a side surface of the gate trench.

9 . A semiconductor device according to claim 8 , wherein the first column is in contact with the bottom surface of the gate trench.

10 . A semiconductor device according to claim 8 , wherein the gate trench includes a plurality of gate trenches side by side, and
wherein a portion of the second semiconductor layer is formed between opposite side surfaces of two adjacent gate trenches.

11 . A semiconductor device according to claim 8 , wherein the first column is spaced apart from the bottom surface of the gate trench.

Assignees

• Renesas Electronics Corp

Inventors

• Shimomura Akihiro
• Sawada Masami

Classifications

• H10D62/051

  Forming charge compensation regions, e.g. superjunctions · CPC title

• H10D64/2527

  for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D30/665

  having edge termination structures · CPC title