Reconstituted substrate structure and fabrication methods for heterogeneous packaging integration

Patent metadata

Field	Value
Publication number	US-2024021533-A1
Application number	US-202318362433-A
Country	US
Kind code	A1
Filing date	Jul 31, 2023
Priority date	May 10, 2019
Publication date	Jan 18, 2024
Grant date	—

Abstract

The present disclosure relates to thin-form-factor reconstituted substrates and methods for forming the same. The reconstituted substrates described herein may be utilized to fabricate homogeneous or heterogeneous high-density 3D integrated devices. In one embodiment, a silicon substrate is structured by direct laser patterning to include one or more cavities and one or more vias. One or more semiconductor dies of the same or different types may be placed within the cavities and thereafter embedded in the substrate upon formation of an insulating layer thereon. One or more conductive interconnections are formed in the vias and may have contact points redistributed to desired surfaces of the reconstituted substrate. The reconstituted substrate may thereafter be integrated into a stacked 3D device.

First claim

What is claimed is:

1 . A method of forming a stacked semiconductor device, comprising:
placing a first dielectric film over a semiconductor package, the semiconductor package comprising:
a first semiconductor die disposed within a first cavity of a first substrate and embedded within a first insulating layer, the first insulating layer disposed over a first side and a second side of the first substrate and contacting each side of the first semiconductor die, the first substrate comprising a material to be selected from a group comprising at least one of: silicon or glass; and
a first conductive interconnection disposed within a first via of the first substrate and extending from at least the first side to the second side of the first substrate, wherein the first insulating layer is disposed between the first conductive interconnection and a sidewall of the first via;
positioning a second substrate over the first dielectric film, the second substrate comprising a second cavity and a second via formed therein, the second substrate comprising a material to be selected from a group comprising silicon or glass; placing a second semiconductor die within the second cavity formed in the second substrate; placing a second dielectric film over the second substrate, wherein the second substrate is disposed between the second dielectric film and the first dielectric film; laminating the first and second dielectric films to form a second insulating layer, the second insulating layer embedding the second semiconductor die within the second cavity; and forming a second conductive interconnection within the second via.

2 . The method of claim 1 , wherein the forming the second conductive interconnection comprises:
laser ablating a hole in the second insulating layer disposed within the second via; and forming a metal layer over a surface of the hole in the second insulating layer.

3 . The method of claim 2 , wherein the forming the second conductive interconnection further comprises:
forming a molybdenum adhesion layer and a copper seed layer over the surface of the hole prior to forming the metal layer.

4 . The method of claim 2 , wherein the laser ablation exposes a surface of the first conductive interconnection through the hole, and wherein the second conductive interconnection is electrically coupled to the first conductive interconnection.

5 . The method of claim 2 , wherein the forming the metal layer comprises electroplating or electroless deposition.

6 . The method of claim 2 , wherein the second conductive interconnection extends at least from a first surface to a second surface of the second substrate.

7 . The method of claim 1 , wherein the first and the second semiconductor dies are of different types.

8 . The method of claim 1 , wherein the first and the second semiconductor dies are of the same type.

9 . The method of claim 8 , wherein the first and second semiconductor dies are DRAM dies and the stacked semiconductor device is a stacked DRAM device.

10 . The method of claim 1 , wherein the first insulating layer and the second insulating layer comprise the same material.

11 . The method of claim 10 , wherein the first insulating layer and the second insulating comprise an epoxy resin material having ceramic fillers.

12 . The method of claim 1 , wherein the second insulating layer comprises a polyimide material.

13 . A method of forming a stacked semiconductor device, comprising:
placing a first dielectric film over a semiconductor package, the semiconductor package comprising:
a first plurality of semiconductor dies disposed within one or more first cavities of a first substrate and embedded within a first insulating layer, the first insulating layer disposed over a first side and a second side of the first substrate and contacting each side of each of the first plurality of semiconductor dies, the first substrate comprising a material to be selected from a group comprising at least one of: silicon or glass; and
a first plurality of conductive interconnections disposed within a first plurality of vias of the first substrate and extending from at least the first side to the second side of the first substrate, wherein the first insulating layer is disposed between the each of the first plurality of conductive interconnection and surfaces of the first plurality of vias;
positioning a second substrate over the first dielectric film, the second substrate comprising one or more second cavities and a second plurality of vias formed therein, the second substrate comprising a material to be selected from a group comprising silicon or glass; placing a second plurality of semiconductor dies within the one or more second cavities formed in the second substrate; placing a second dielectric film over the second substrate, wherein the second substrate is disposed between the second dielectric film and the first dielectric film; laminating the first and second dielectric films to form a second insulating layer, the second insulating layer embedding the second plurality of semiconductor dies within the one or more second cavities and filling each of the second plurality of vias; laser ablating a plurality of holes in the second insulating layer, each of the plurality of holes formed through a portion of the second insulating layer filling one of the second plurality of vias; and forming a second plurality of conductive interconnections, each of the second plurality of conductive interconnections formed over a surface of one of the plurality of holes.

14 . The method of claim 13 , wherein the forming the second plurality of conductive interconnections further comprises:
forming a molybdenum adhesion layer and a copper seed layer over the surfaces of each of the plurality of holes.

15 . The method of claim 13 , wherein the laser ablation exposes a surface of at least one of the first plurality of conductive interconnections through the plurality of holes, and wherein at least one of the second plurality of conductive interconnections is electrically coupled to the at least one of the first plurality of conductive interconnections.

16 . The method of claim 13 , wherein the forming the second plurality of conductive interconnections comprises electroplating or electroless deposition of the second plurality of conductive interconnections.

17 . The method of claim 13 , wherein at least one of the second plurality of conductive interconnections extends at least from a first surface to a second surface of the second substrate.

18 . The method of claim 13 , wherein at least one of the first plurality of semiconductor dies and at least one of the second plurality of semiconductor dies are of different types.

19 . The method of claim 13 , wherein at least one of the first plurality of semiconductor dies and at least one of the second plurality of semiconductor dies are of the same type.

20 . A method of forming a stacked DRAM device, comprising:
placing a first dielectric film over a semiconductor package, the semiconductor package comprising:
a first DRAM die disposed within a first cavity of a first substrate and embedded within a first insulating layer, the first insulating layer disposed over a first side and a second side of the first substrate and contacting each side of the first DRAM die, the first substrate comprising a material to be selected from a group comprising at least one of: silicon or glass; and
a first conductive interconnection disposed within a first via of t

Assignees

• Applied Materials Inc

Inventors

• Chen Han-Wen
• Verhaverbeke Steven
• See Guan Huei
• Park Giback
• Cellere Giorgio
• Tonini Diego
• Dicaprio Vincent
• Cho Kyuil

Classifications

• H10W72/07236

  Soldering or alloying · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title