Epitaxial substrate surfaces for semiconductor material growth and improved smooth semiconductor surfaces for higher channel mobility through the formation and removal of reactive layers

Patent metadata

Field	Value
Publication number	US-2024021428-A1
Application number	US-202318352175-A
Country	US
Kind code	A1
Filing date	Jul 13, 2023
Priority date	Jul 13, 2022
Publication date	Jan 18, 2024
Grant date	—

Abstract

A method for processing a surface, comprising obtaining a substrate comprising an epitaxially grown semiconductor; reacting a surface of the semiconductor and/or a surface of a dielectric layer on the semiconductor, with a reactant comprising a gas or a plasma, to form a reactive layer on the dielectric layer and/or the semiconductor, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer or the semiconductor; and processing (e.g., removing, modifying, and/or chemically reducing) the reactive layer, wherein the processing at least smoothens, controls defects at, improves the electrical properties of, or the optical properties of, the surface

First claim

What is claimed is:

1 . A method for processing a surface, comprising:
(a) obtaining a substrate comprising an epitaxially grown semiconductor or an ordered substrate template for subsequent epitaxial growth of a semiconductor; (b) reacting a surface of the semiconductor and/or a surface of a dielectric layer on the semiconductor, with a reactant comprising a gas, a plasma, or a fluid, to form a reactive layer on the dielectric layer and/or the semiconductor, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer or the semiconductor; and (c) processing (e.g., removing and/or chemically reducing) the reactive layer, wherein the processing at least smoothens, or controls defects at, the surface.

2 . The method of claim 1 , wherein the processing comprises reacting the reactive layer with an agent that induces a re-arrangement of chemical bonds between constituents of the reactive layer and wherein the re-arrangement removes at least part of the constituents of the reactive layer from the surface.

3 . The method of claim 2 , wherein the reacting comprises projecting the agent onto the surface with an energy:
below that required for physical sputtering of the surface using the agent so that the material is not ejected from the substrate by a physical sputtering process, and sufficient to act as a catalyst for the re-arrangement.

4 . The method of claim 2 , wherein the agent comprises ions.

5 . The method of claim 1 , wherein the processing comprises accelerating ions onto the surface and selecting an angle of incidence of the ions with respect to a surface normal so as to smoothen or remove the defects from the surface.

6 . The method of claim 1 , wherein the processing comprises accelerating ions onto the surface and at least one of:
selecting a temperature of the processing, selecting an angle of incidence of the processing, selecting a composition of the reactant, or selecting an angle of incidence of the ions onto the surface, and so as to control anisotropy or isotropy of removal of the reactive layer.

7 . The method of claim 6 , wherein the processing comprises removing the reactive layer along a direction having a larger component parallel to the surface of the reactive layer, as compared to the component normal to the surface.

8 . The method of claim 1 , wherein the formation of the reactive layer comprises and at least one of:
selecting a temperature of the processing, or selecting a composition of the reactant, so as to control anisotropy or isotropy of formation of the reactive layer.

9 . The method of claim 1 , wherein the processing comprises chemical sputtering or wet etching with a liquid wet etchant.

10 . The method of claim 1 , wherein the reactive layer comprises valleys having sidewalls and the processing etches the valleys laterally through the sidewalls so as to planarize the surface and remove or connect the valleys.

11 . The method of claim 9 , wherein the valleys have a height and width in a range of 1-1000 nm.

12 . The method of claim 1 , wherein the reactant comprises at least one of a halogen that halogenates the surface, a halogen combined with carbon, a mixture of halogens, a sulphide so as to form the reactive layer comprising a sulphide, hydrogen or a hydride so as to form the reactive layer comprising a hydride, a nitride or nitrogen so as to form the reactive layer comprising a nitride, or oxygen or an oxide so as to form the reactive layer comprising an oxide.

13 . The method of claim 1 , wherein the reactive layer comprises chlorinated silicon, the reactant comprises chlorine, bromine, or boron trichloride, and the agent comprises argon, neon, krypton, or helium ions.

14 . The method of claim 1 , further comprising repeating steps (b) and (c) so as to perform a plurality of etching cycles each comprising the step (b) and the step (c), wherein:
the cycles include one or more first cycles and a second cycle subsequent to the first cycle, the second cycle forms the reactive layer that is thinner as compared to the reactive layer formed in the first cycles, so that the processing in the second cycle processes the reactive layer with a finer resolution as compared to the etching in one or more the first cycles, and the reactive layer in one or more of the first cycles is incrementally decreased in the (n+1)th first cycle as compared to the nth first cycle (the thickness of the reactive layer in one or more of the first cycles can be the same or gradually decreased).

15 . The method of claim 14 where the final cycle terminates without removal of the reactive layer.

16 . The method of claim 15 wherein:
the composition and/or thickness of the final reactive layer which remains is different than the reactive layer before it which was at least partially removed, and/or
the composition and/or thickness of the final reactive layer is chosen to make the semiconductor substrate or layer be more amenable to subsequent processing, and/or
the composition and/or thickness of the final reactive layer is chosen to enhance the electrical or optical properties of the final device.

17 . The method of claim 16 where the electrical property improved is at least one of carrier mobility or contact resistance.

18 . The method of claim 15 , comprising forming a structure wherein:
the final reactive layer acts as passivation to reduce or prevent change in air, and/or the final reactive layer comprises a halogen, nitrogen, carbon, sulphur, or hydrogen, and/or the final reactive layer reduces or prevents oxidation of the semiconductor, and/or the final reactive layer is incorporated into the final device, and/or the final reactive layer is made to be more amenable to removal in situ prior to a subsequent epitaxial growth step which results in a higher quality epitaxial growth than would have been achieved without the final reactive layer.

19 . The method of claim 1 , wherein the semiconductor comprises:
silicon or a compound that principally contains elements from group III and group V from the periodic table (a III-V material) or a compound that principally contains elements from group II and group VI of the periodic table (II-VI material), Si, Ge, or a superlattice of any of these materials, and/or the semiconductor is doped.

20 . The method of claim 1 , wherein the processing controls a dopant profile at the surface.

21 . An apparatus for etching a substrate, comprising:
one or more reactor tools reacting a reactant with a surface of a dielectric layer or semiconductor so as to form a reactive layer on the dielectric layer or the semiconductor, wherein the reactant comprises a gas or plasma, wherein the reactive layer comprises a chemical compound including the reactant and elements of the dielectric layer or the semiconductor; and one or more tools outputting a treatment or processing agent for processing the reactive layers so as to at least smoothen, or control defects at, the surface.

22 . A wafer, comprising:
a processed surface of an epitaxial material comprising a semiconductor, wherein: the processed surface comprises fewer defects as compared to the surface prior to processing compared to in a bulk of the substrate, and the processed surface has a root mean square surface roughness of less than 1 nanometer over an entirety of the surface area of the wafer, and the epitaxial layer is single crystalline, and wherein

Assignees

• California Inst Of Techn
• Univ Southern California

Inventors

• Greer Harold Frank
• Kapadia Rehan
• Sarkar Debargyha

Classifications

• H10W20/425

  Barrier, adhesion or liner layers · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title

• H10P14/24 Primary

  using chemical vapour deposition [CVD] · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P90/00 Primary

  Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement · CPC title