Nonvolatile memory device and method of detecting defective memory cell block of nonvolatile memory device

Patent metadata

Field	Value
Publication number	US-2024021255-A1
Application number	US-202318356522-A
Country	US
Kind code	A1
Filing date	Jul 21, 2023
Priority date	Aug 12, 2020
Publication date	Jan 18, 2024
Grant date	—

Abstract

A method of detecting, by a nonvolatile memory system, a defective memory cell block from among memory cell blocks, includes performing, after performing an erase operation, a read operation on at least some memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage that distinguishes an off-cell on which no data is written from an on-cell on which data is written; counting a number of hard off-cells having a higher threshold voltage than the off-cell detection voltage from among the memory cells based on a result of performing the read operation; and identifying whether the target memory cell block is a defective memory cell block based on the number of counted hard off-cells.

First claim

What is claimed is:

1 . A memory device comprising:
a voltage generator is configured to perform, after an erase operation, a read operation on one or more memory cells included in a target memory cell block based on an off-cell detection voltage that is different from a read reference voltage; and a control circuit, wherein the control circuit is configured to: output a first signal indicating a number of hard off-cells counted having a higher threshold voltage than the off-cell detection voltage among the one or more memory cells based on a result of performing the read operation; and receive a second signal indicating that whether the target memory cell block is a defective memory cell block based on the number of hard off-cells.

2 . The memory device of claim 1 , wherein the voltage generator further configured to output, as the off-cell detection voltage, a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard off-cell.

3 . The memory device of claim 1 , further comprises:
a memory cell array in which a plurality of word lines are connected to memory cells of a target cell string such that a voltage is applied to the memory cells; a row decoder configured to apply the off-cell detection voltage to a target memory cell among the memory cells via a target word line from among the plurality of word lines; and a sensing amplifier configured to receive an output current from the target memory cell based on the off-cell detection voltage.

4 . The memory device of claim 3 , wherein the sensing amplifier outputs a signal indicating whether the target memory cell is a hard off-cell, based on the output current.

5 . The memory device of claim 4 , wherein the sensing amplifier outputs a signal indicating that the target memory cell is the hard off-cell based on the output current being less than a threshold current.

6 . The memory device of claim 1 , further comprises a pager buffer configured to count the number of hard off-cells from among the one or more memory cells based on a result of the performing of the read operation.

7 . The memory device of claim 1 , wherein the control circuit is further configured to:
output a third signal indicating a result of the performing of the read operation; and receive a fourth signal indicating that whether the target memory cell block is a defective memory cell block based on the result of the performing of the read operation.

8 . The memory device of claim 1 , further comprises an off-cell information storage block configured to store a block address, a string select line (SSL) address, and information of a reference number of off-cells corresponding to the block address and the SSL address,
wherein the control circuit is configured to output a fifth signal indicating the reference number of off-cells.

9 . The memory device of claim 8 , wherein, in the off-cell information storage block, an initial number of off-cells corresponding to each string select line of a plurality of memory cell blocks is stored to correspond to the block address and the SSL address.

10 . The memory device of claim 8 , wherein the control circuit is further configured to receive the second signal indicating the target memory cell block as the defective memory cell block based on the number of hard off-cells exceeding the reference number of off-cells.

11 . A memory device comprising:
a voltage generating circuit configured to apply an off-cell detection voltage that is different from a read reference voltage to a target memory cell to perform a hard off-cell detection operation on the target memory cell after the memory device performs an erase operation; a sensing amplifier configured to receive an output current from a target cell string based on the off-cell detection voltage; and a control circuit configured to output a first signal indicating that the target memory cell is a hard off-cell based on the output current of the target memory cell being less than a threshold current.

12 . The memory device of claim 11 , wherein the voltage generating circuit further configured to output, as the off-cell detection voltage, a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard off-cell.

13 . The memory device of claim 11 , further comprises:
a memory cell array in which a plurality of word lines are connected to memory cells of the target cell string such that a voltage is applied to the memory cells; and a row decoder configured to apply the off-cell detection voltage to the target memory cell among the memory cells via a target word line from among the plurality of word lines.

14 . The memory device of claim 11 , wherein the control circuit further configured to receive a second signal indicating that whether a target memory cell block comprising the target memory cell is a defective memory cell block generated based on the first signal.

15 . The memory device of claim 14 , further comprises an off-cell information storage block configured to store a block address, a string select line (SSL) address, and information of a reference number of off-cells corresponding to the block address and the SSL address,
wherein the control circuit is configured to output a third signal indicating the reference number of off-cells.

16 . A method of detecting an hard off-cell comprising:
applying an off-cell detection voltage that is different from a read reference voltage to a target memory cell to perform a hard off-cell detection operation on the target memory cell after a memory device performs an erase operation; sensing an output current from the target memory cell based on the off-cell detection voltage; and outputting a first signal indicating that the target memory cell is the hard off-cell based on the output current of the target memory cell being less than a threshold current.

17 . The method of claim 16 , wherein the applying the off-cell detection voltage comprises setting, as the off-cell detection voltage, a value between a threshold voltage level of an erased memory cell and a threshold voltage level of a hard off-cell.

18 . The method of claim 16 , wherein the applying the off-cell detection voltage comprises applying the off-cell detection voltage to each of a plurality of word lines connected to a target memory cell block comprising the target memory cell; and
the sensing the output current comprises measuring an output current from a cell string connected to the target memory cell block.

19 . The method of claim 16 , further comprises receiving a second signal indicating that whether a target memory cell block comprising the target memory cell is a defective memory cell block generated based on the first signal.

20 . The memory device of claim 19 , further comprises outputting a third signal indicating a reference number of off-cells.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Myungnam
• Kim Daehan
• Jung Wontaeck

Classifications

• G11C16/3445 Primary

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title

• G11C16/16

  for erasing blocks, e.g. arrays, words, groups · CPC title

• G11C16/3409

  Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title