Systems and techniques for accessing multiple memory cells concurrently

Patent metadata

Field	Value
Publication number	US-2024013833-A1
Application number	US-202318208103-A
Country	US
Kind code	A1
Filing date	Jun 9, 2023
Priority date	Dec 19, 2018
Publication date	Jan 11, 2024
Grant date	—

Abstract

Techniques are provided for accessing two memory cells of a memory tile concurrently. A memory tile may include a plurality of self-selecting memory cells addressable using a row decoder and a column decoder. A memory controller may access a first self-selecting memory cell of the memory tile using a first pulse having a first polarity to the first self-selecting memory cell. The memory controller may also access a second self-selecting memory cell of the memory tile concurrently with accessing the first self-selecting memory cell using a second pulse having a second polarity different than the first polarity. The memory controller may determine characteristics of the pulses to mitigate disturbances of unselected self-selecting memory cells of the memory tile.

First claim

1 . (canceled)

2 . A method, comprising:
identifying a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity; identifying a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity; reading the first memory cell; and reading the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.

3 . The method of claim 2 , further comprising:
determining that the first memory cell is coupled with different access lines than the second memory cell, wherein reading the second memory cell concurrently with reading the first memory cell is based at least in part on determining that the first memory cell is coupled with different access lines than the second memory cell.

4 . The method of claim 2 , further comprising:
applying a first voltage having the first polarity to a first digit line coupled with the first memory cell based at least in part on the first read pulse having the first polarity; and applying a second voltage having the second polarity to a second digit line coupled with the second memory cell based at least in part on the second read pulse having the second polarity.

5 . The method of claim 2 , further comprising:
applying a first voltage having the second polarity to a first digit line coupled with the first memory cell based at least in part on the first read pulse having the first polarity; and applying a second voltage having the first polarity to a second digit line coupled with the second memory cell based at least in part on the second read pulse having the second polarity.

6 . The method of claim 2 , wherein the first polarity is opposite the second polarity such that the first section of memory cells is configured to be read with a positive polarity read pulse and the second section of memory cells is configured to read with a negative polarity read pulse.

7 . The method of claim 2 , wherein a memory cell of the memory tile is comprises a chalcogenide material having a non-uniform distribution of ions to indicate a logic state of one memory cell of the first section of memory cells.

8 . The method of claim 2 , wherein one or more trim parameters for the first section of memory cells are independent of one or more trim parameters for the second section of memory cells.

9 . The method of claim 2 , wherein the memory tile includes more than one deck of memory cells.

10 . An electronic memory apparatus, comprising:
a memory tile having a first section of memory cells and a second section of memory cells, wherein the memory cells of the first section are configured to be read in response to application of a first read pulse having a first polarity and the memory cells of the second section are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity; a first sense component coupled with the first section of memory cells of the memory tile and configured to identify a logic state of one memory cell of the first section of memory cells based at least in part on the first read pulse having the first polarity; and a second sense component coupled with the second section of memory cells of the memory tile and configured to identify the logic state of one memory cell of the second section of memory cells based at least in part on the second read pulse having the second polarity.

11 . The electronic memory apparatus of claim 10 , wherein the memory cells of the first section of memory cells are coupled with different access lines than the memory cells of the second section of memory cells, and wherein the memory cells of the first section of memory cells are configured to be read concurrently with the memory cells of the second section of memory cells.

12 . The electronic memory apparatus of claim 10 , further comprising:
a first voltage source coupled with digit lines of the first section, the first voltage source configured to supply at least a portion of the first read pulse having the first polarity; and a second voltage source coupled with digit lines of the second section, the second voltage source configured to supply at least a portion of the second read pulse having the second polarity.

13 . The electronic memory apparatus of claim 10 , further comprising:
a first voltage source coupled with one or more digit lines of the first section, the first voltage source configured to supply at least a portion of the first read pulse having the second polarity; and a second voltage source coupled with one or more digit lines of the second section, the second voltage source configured to supply at least a portion of the second read pulse having the second polarity.

14 . The electronic memory apparatus of claim 10 , wherein the first polarity is different than the second polarity.

15 . The electronic memory apparatus of claim 10 , wherein a memory cell of the memory tile is formed of a chalcogenide material configured to use a non-uniform distribution of ions to indicate the logic state.

16 . The electronic memory apparatus of claim 10 , wherein one or more trim parameters for the first section of memory cells are independent of one or more trim parameters for the second section of memory cells.

17 . The electronic memory apparatus of claim 10 , wherein the first sense component and the second sense component are positioned under a footprint of the memory tile.

18 . The electronic memory apparatus of claim 10 , wherein the memory tile includes more than one deck of memory cells.

19 . A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
identify a first memory cell of a first section of a memory tile to be read, wherein memory cells in the first section of the memory tile are configured to be read in response to application of a first read pulse having a first polarity; identify a second memory cell of a second section of the memory tile to read, wherein memory cells in the second section of the memory tile are configured to be read in response to application of a second read pulse having a second polarity different than the first polarity; read the first memory cell; and read the second memory cell concurrently with reading the first memory cell based at least in part on identifying the first memory cell of the first section and the second memory cell of the second section.

20 . The non-transitory computer-readable medium of claim 19 , wherein the instructions are further executable by the one or more processors to:
determine that the first memory cell is coupled with different access lines than the second memory cell, wherein reading the second memory cell concurrently with reading the first memory cell is based at least in part on determining that the first memory cell is coupled with different access lines than the second memory cell.

21 . The non-transitory computer-readable medium of claim 19 , wherein the instructions are further executable by the one or more processors to:
apply a first v

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• G11C13/003 Primary

  Cell access · CPC title

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G11C13/0061

  Timing circuits or methods · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title