Corrugated metal oxide semiconductor transistor

Patent metadata

Field	Value
Publication number	US-2023411452-A1
Application number	US-202217829009-A
Country	US
Kind code	A1
Filing date	May 31, 2022
Priority date	May 31, 2022
Publication date	Dec 21, 2023
Grant date	—

Abstract

A method forms a semiconductor device with a substrate including semiconductor material formed to include plural corrugation members, each member including a top surface, and a first and second sidewall extending from the top surface to a lower surface. The method forms a contiguous transistor source extending through a first volume of each of the corrugation members and a first lower surface volume and a contiguous transistor drain extending through a second volume of each of the corrugation members and a second lower surface volume. Both source and drain are formed by initially diffusing a dopant in a uniform manner normal to various portions, some non-coplanar, of the source and drain, respectively.

First claim

What is claimed is:

1 . A method of forming a semiconductor device, comprising:
providing a substrate including at least a portion of a semiconductor material; forming a plurality of corrugation members of the semiconductor material, each corrugation member in the plurality of corrugation members including a top surface, and a first and second sidewall extending from the top surface to a lower surface; forming a contiguous transistor source extending through a first volume of each of the corrugation members and a first lower surface volume extending into the semiconductor material from the lower surface by initially diffusing a dopant in a uniform manner normal to a first portion of the top surface, a first portion of the first sidewall, a first portion of the second sidewall, and a first portion of the lower surface; and forming a contiguous transistor drain extending through a second volume of each of the corrugation members and a second lower surface volume extending into the semiconductor material from the lower surface by initially diffusing the dopant in a uniform manner normal to a second portion of the top surface, a second portion of the first sidewall, a second portion of the second sidewall, and a second portion of the lower surface.

2 . The method of claim 1 :
wherein the forming a contiguous transistor source diffuses to a same diffusion length at and normal from a respective midpoint of each of the first portion of the top surface, the first portion of the first sidewall, the first portion of the second sidewall, and the first portion of the lower surface; and wherein the forming a contiguous transistor drain diffuses to the same diffusion length at and normal from a respective midpoint of each of the second portion of the top surface, the second portion of the second sidewall, the second portion of the second sidewall, and the second portion of the lower surface.

3 . The method of claim 2 wherein each respective midpoint is along a dimension extending from a first corrugation member of the plurality of corrugation members to a second corrugation member of the plurality of corrugation members, and halfway between opposing edges, in the dimension, of the respective surface.

4 . The method of claim 1 wherein each of the steps of forming a contiguous transistor source and forming a contiguous transistor drain includes forming a masking stack including at least three masking layers.

5 . The method of claim 4 wherein the masking stack includes a photoresist layer, a pattern transfer layer, and a pattern receiving layer.

6 . The method of claim 1 and further including:
in a first step, forming metalization using silicides adjacent selected portions of the top surface of each corrugation member corresponding to the contiguous transistor source and the contiguous transistor drain; and
in a second step, forming metalization using conformal metal silicide film adjacent selected portions of the first and second sidewall of each corrugation member corresponding to the contiguous transistor source and the contiguous transistor drain.

7 . The method of claim 6 wherein the silicides include self-aligned silicides.

8 . The method of claim 6 wherein the first step and the second step occur separately.

9 . The method of claim 1 and further including forming metalization using conformal metal film adjacent selected portions of the first and second sidewall of each corrugation member corresponding to the contiguous transistor source and the contiguous transistor drain.

10 . A method of forming a semiconductor device, comprising:
providing a substrate including at least a portion of a semiconductor material; forming a corrugation member in the semiconductor material, the corrugation member including a top surface, a first lateral portion extending from the top surface to a first lower surface of the semiconductor material, and a second lateral portion extending from the top surface to a second lower surface of the semiconductor material; using a first mask created from a first multilayer stack process to form a transistor body in the semiconductor material, the transistor body having a first conductivity type; using a second mask created from a second multilayer stack process to form a transistor source in the semiconductor material, the transistor source having a second conductivity type complementary to the first conductivity type, the transistor source having a common diffusion length at a midpoint in each of a respective second portion of the top surface, a second portion of the first lateral portion, a second portion of the second lateral portion, a second portion in the first lower surface, and a second portion in the second lower surface; and using a third mask created from a third multilayer stack process to form a transistor drain in the semiconductor material, the transistor drain having the second conductivity type, the transistor drain having the common diffusion length at a midpoint in each of a respective third portion of the top surface, a third portion of the first lateral portion, a third portion of the second lateral portion, a third portion in the first lower surface, and a third portion in the second lower surface.

11 . The method of claim 10 wherein the first, second, and third multilayer stack processes each include:
forming a photoresist layer on a pattern transfer layer on a pattern receiving layer;
forming a pattern in the photoresist layer;
etching the pattern transfer layer using the pattern in the photoresist layer;
removing the photoresist layer;
after removing the photoresist layer, etching the pattern receiving layer using the pattern transfer layer; and
removing the pattern transfer layer.

12 . The method of claim 11 wherein the pattern receiving layer includes a silicon nitride dopant blocking layer or a silicon oxynitride dopant blocking layer.

13 . The method of claim 10 wherein the step to form a transistor source and the step to form a transistor drain include a concurrent plasma doping step.

14 . The method of claim 10 wherein the step to form a transistor source and the step to form a transistor drain include a concurrent atomic layer deposition step.

15 . The method of claim 10 wherein the step to form a transistor source and the step to form a transistor drain include a concurrent vapor phase doping step.

16 . The method of claim 10 wherein the step to form a transistor source and the step to form a transistor drain include a concurrent chemical vapor deposition doping step.

17 . The method of claim 10 wherein the step to form a transistor source and the step to form a transistor drain include a concurrent gas phase deposition doping step.

18 . The method of claim 10 wherein the step to form a transistor source and the step to form a transistor drain include a concurrent solid sublimation doping step.

19 . The method of claim 10 and further including:
in a first step, forming metalization adjacent a first portion of the transistor source and a first portion of the transistor drain in a first dimension; and
in a second step, separate from the first step, forming metalization adjacent a second portion of the transistor source and a second portion of the transistor drain in a second dimension that differs from the first dimension.

20 . A semiconductor device, comprising:
a substrate including at least a portion of a semiconductor material; a corrugation member, the corrugation member including a top surface of

Assignees

• Texas Instruments Inc

Inventors

• Haynie Sheldon Douglas
• Sadovnikov Alexei
• Goodlin Brian

Classifications

• H10D30/6212

  having fin-shaped semiconductor bodies having non-rectangular cross-sections · CPC title

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title

• H10D30/608

  having non-planar bodies, e.g. having recessed gate electrodes · CPC title