Fragment compression for coarse pixel shading

Patent metadata

Field	Value
Publication number	US-2023386130-A1
Application number	US-202318305511-A
Country	US
Kind code	A1
Filing date	Apr 24, 2023
Priority date	Apr 21, 2017
Publication date	Nov 30, 2023
Grant date	—

Abstract

One embodiment provides for a graphics processing unit comprising a processing cluster to perform multi-rate shading via coarse pixel shading and output shaded coarse pixels for processing by a post-shader pixel processing pipeline.

First claim

What is claimed is:

1 . A graphics processing unit comprising:
a processing cluster to perform multi-rate shading via coarse pixel shading, wherein the processing cluster includes circuitry to vary a shading rate via a coarse pixel shading operation on a coarse pixel quad fragment to generate a coarse pixel quad and output the coarse pixel quad; and a post-shader pixel pipeline including circuitry to:
receive the coarse pixel quad from the processing cluster;
perform coarse pixel operations on multiple coarse pixels within the coarse pixel quad via a pixel processing unit of the post-shader pixel pipeline; and
write, via the post-shader pixel pipeline, a processed coarse pixel quad to a render cache.

2 . The graphics processing unit as in claim 1 , wherein the processing cluster is to write constituent pixel quads of the coarse pixel quad to the render cache.

3 . The graphics processing unit as in claim 2 , wherein to receive the coarse pixel quad from the processing cluster, the post-shader pixel pipeline is to read the constituent pixel quads of the coarse pixel quad from the render cache.

4 . The graphics processing unit as in claim 3 , wherein the post-shader pixel pipeline includes circuitry to perform cacheline aware fragment compression on the constituent pixel quads of the coarse pixel quad and process the constituent pixel quads as a coarse pixel in response to a determination that the constituent pixel quads cover a cacheline of the render cache.

5 . The graphics processing unit as in claim 4 , wherein post-shader pixel pipeline includes circuitry to perform cacheline aware fragment expansion on the coarse pixel quad to expand the coarse pixel quad into the constituent pixel quads in response to a determination that the coarse pixel quad is not fully lit.

6 . The graphics processing unit as in claim 4 , wherein the post-shader pixel pipeline includes circuitry to perform cacheline aware fragment expansion on a coarse pixel quad to expand the coarse pixel quad into the constituent pixel quads in response to a determination that the coarse pixel quad does not cover a full cacheline of the render cache.

7 . The graphics processing unit as in claim 4 , wherein the coarse pixel quad is determined to cover the cacheline of the render cache based on a size of a cacheline and a coarse pixel scaling factor.

8 . The graphics processing unit as in claim 7 , wherein the processing cluster includes circuitry to adjust the coarse pixel scaling factor of a coarse pixel during the coarse pixel shading.

9 . The graphics processing unit as in claim 8 , wherein processing cluster is to implement multi-rate shading via adjustment of the coarse pixel scaling factor.

10 . A data processing system comprising:
a display device; a memory device to store pixel data for display via the display device; and a graphics processor to generate the pixel data, the graphics processor including: a graphics processor cache memory; and a processing cluster to perform multi-rate shading via coarse pixel shading, wherein the processing cluster includes circuitry to vary a shading rate via a coarse pixel shading operation on a coarse pixel quad fragment to generate a coarse pixel quad and output the coarse pixel quad; and a post-shader pixel pipeline including circuitry to:
receive the coarse pixel quad from the processing cluster;
perform coarse pixel operations on multiple coarse pixels within the coarse pixel quad via a pixel processing unit of the post-shader pixel pipeline; and
write, via the post-shader pixel pipeline, a processed coarse pixel quad to a render cache.

11 . The data processing system as in claim 10 , wherein the graphics processor is to write the processed coarse pixel quad evicted to the processor cache memory to the memory device as the pixel data.

12 . The data processing system as in claim 10 , wherein the processing cluster is to write constituent pixel quads of the coarse pixel quad to the render cache.

13 . The data processing system as in claim 12 , wherein to receive the coarse pixel quad from the processing cluster, the post-shader pixel pipeline is to read the constituent pixel quads of the coarse pixel quad from the render cache.

14 . The data processing system as in claim 13 , wherein the post-shader pixel pipeline includes circuitry to perform cacheline aware fragment compression on the constituent pixel quads of the coarse pixel quad and process the constituent pixel quads as a coarse pixel in response to a determination that the constituent pixel quads cover a cacheline of the render cache.

15 . The data processing system as in claim 14 , wherein post-shader pixel pipeline includes circuitry to perform cacheline aware fragment expansion on the coarse pixel quad to expand the coarse pixel quad into the constituent pixel quads in response to a determination that the coarse pixel quad is not fully lit.

16 . The data processing system as in claim 14 , wherein the post-shader pixel pipeline includes circuitry to perform cacheline aware fragment expansion on a coarse pixel quad to expand the coarse pixel quad into the constituent pixel quads in response to a determination that the coarse pixel quad does not cover a full cacheline of the render cache.

17 . The data processing system as in claim 14 , wherein the coarse pixel quad is determined to cover the cacheline of the render cache based on a size of a cacheline and a coarse pixel scaling factor.

18 . The data processing system as in claim 17 , wherein the processing cluster includes circuitry to implement multi-rate shading via adjustment of the coarse pixel scaling factor.

19 . A method of post shader pixel processing on a post-shader pixel pipeline, the method comprising:
receiving a coarse pixel quad from a processing cluster configured to perform a multi-rate shading via coarse pixel shading operations on coarse pixel quad fragments to generate coarse pixel quads; varying a shading rate by performing coarse pixel operations on multiple coarse pixels within the coarse pixel quad via a pixel processing unit of the post-shader pixel pipeline; writing via the post-shader pixel pipeline, a processed coarse pixel quad to a render cache; evicting the processed coarse pixel quad from the render cache to a graphics processor cache memory as a coarse pixel; and writing the processed coarse pixel quad evicted to the processor cache memory to a memory device as pixel data.

20 . The method as in claim 19 , wherein receiving the coarse pixel quad from the processing cluster includes:
reading constituent pixel quads of the coarse pixel quad from the render cache; performing cacheline aware fragment compression on the constituent pixel quads of the coarse pixel quad; and processing the constituent pixel quads as a coarse pixel in response to a determination that the constituent pixel quads cover a cacheline of the render cache.

Assignees

• Intel Corp

Inventors

• Surti Prasoonkumar
• Appu Abhishek R
• Dasgupta Subhajit
• Mysore Srivallaba
• Norris Michael J
• Ranganathan Vasanth
• Ray Joydeep

Classifications

• G06T15/80 Primary

  Shading · CPC title

• G06T1/20

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T1/60

  Memory management · CPC title

• G06T15/005

  General purpose rendering architectures · CPC title

• G06T2210/52

  Parallel processing · CPC title