Memory module having volatile and non-volatile memory subsystems and method of operation

Patent metadata

Field	Value
Publication number	US-2023385192-A1
Application number	US-202318325081-A
Country	US
Kind code	A1
Filing date	May 29, 2023
Priority date	Nov 7, 2013
Publication date	Nov 30, 2023
Grant date	—

Abstract

A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.

First claim

We claim:

1 . A memory module, comprising:
dynamic random access memory (DRAM); Flash memory; a module controller coupled to the DRAM and the Flash memory, the module controller including local memory, wherein the module controller is configurable to: receive data to be transferred from the DRAM to the Flash memory; compute first cyclic redundancy check (CRC) codes for the data; write the data into the Flash memory; read the data from the Flash memory; store the data read from the Flash memory in local memory; transfer the data read from the Flash memory to the DRAM; compute second CRC codes for the data read from the Flash memory and stored in the local memory; compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory; read a data segment of the data transferred to the DRAM from the DRAM, the data segment including the one or more erroneous data bits; correct the one or more erroneous data bits in the data segment read from the DRAM; and write the data segment back into the DRAM.

2 . The memory module of claim 1 , wherein the data to be transferred from the DRAM to the Flash memory includes first data bits and the module controller is further configurable to:
arrange the first data bits into first data sets, whereby each data bit of the first data bits is assigned to at least two intersecting data sets of the first data sets, each data set of the first data sets including a plurality of data bits from the first data bits, and no two datasets of the first data sets have more than one data bit in common; and compute CRC codes for the data by performing error correction coding on each respective data set of the first data sets to obtain respective CRC codes for the respective data set.

3 . The memory module of claim 2 , wherein the data read from the Flash memory includes second data bits corresponding, respectively, to the first data bits, and the module controller is further configurable to:
arrange the second data bits into second data sets, such that the second data sets correspond, respectively, to the first data sets, and data bits in each data set of the first data sets correspond, respectively, to data bits in a corresponding data set of the second data sets; and compute second CRC codes for the data read from the Flash memory by performing error correction coding on each individual data set of the second data sets to obtain individual CRC codes for the individual data set.

4 . The memory module of claim 3 , wherein the module controller is further configurable to:
in response to the CRC codes of a particular data set in the second data sets not matching the CRC codes of a corresponding data set of the first data sets, determine at least one intersecting data set of the second data sets, each of the at least one intersecting data set having CRC codes not matching the CRC codes of a corresponding data set of the first data sets and having one data bit in common with the particular data set; determine one or more erroneous data bits in the second data bits based on the particular data set and the at least one intersecting data set.

5 . A method at a memory module comprising dynamic random access memory (DRAM), Flash memory, and a module controller coupled to the DRAM and the Flash memory, comprising:
receiving data to be transferred from the DRAM to the Flash memory; computing first cyclic redundancy check (CRC) codes for the data; writing the data into the Flash memory; reading the data from the Flash memory; storing the data read from the Flash memory in local memory; transferring the data read from the Flash memory to the DRAM; computing second CRC codes for the data read from the Flash memory and stored in the local memory; comparing the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory; reading a data segment of the data transferred to the DRAM from the DRAM, the data segment including the one or more erroneous data bits; correcting the one or more erroneous data bits in the data segment read from the DRAM; and writing the data segment back into the DRAM.

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R
• Chen Chi She
• Solomon Jeffery C
• Martinez Mario Jesus
• Le Hao
• Choi Soon J

Classifications

• G06F12/0246 Primary

  in block erasable memory, e.g. flash memory · CPC title

• G06F12/08

  in hierarchically structured memory systems, e.g. virtual memory systems · CPC title

• G06F12/0871

  Allocation or management of cache space · CPC title

• G06F3/061

  Improving I/O performance · CPC title

• G11C7/1072

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title