Checkpoint-progress status

Patent metadata

Field	Value
Publication number	US-2023376381-A1
Application number	US-202318316614-A
Country	US
Kind code	A1
Filing date	May 12, 2023
Priority date	May 17, 2022
Publication date	Nov 23, 2023
Grant date	—

Abstract

A method comprising, in response to a power-drop warning, beginning a checkpointing process comprising storing, to a non-volatile memory, execution state associated with data processing operations performed by data processing circuitry. The method also comprises maintaining, in the non-volatile memory, a checkpoint-progress indication to indicate which of multiple sections of the execution state have been stored as part of the checkpointing process.

First claim

What is claimed is:

1 . A method comprising:
in response to a power-drop warning, performing a checkpointing process comprising storing, to a non-volatile memory, execution state associated with data processing operations performed by data processing circuitry; and maintaining, in the non-volatile memory, a checkpoint-progress status to indicate which of multiple sections of the execution state have been stored as part of the checkpointing process.

2 . The method of claim 1 , comprising
in response to a power-restore signal, restoring the sections of the execution state that have been stored as part of the checkpointing process.

3 . The method of claim 1 , wherein
the checkpoint-progress status is maintained in the non-volatile memory by the data processing circuitry executing checkpointing software.

4 . The method of claim 1 , wherein
the checkpointing process is performed by checkpointing circuitry; and the checkpoint-progress status is updated in the non-volatile memory by the checkpointing circuitry.

5 . The method of claim 4 , wherein
the checkpointing circuitry comprises a multi-channel direct memory access (DMA) controller; and the method comprises: configuring the multi-channel DMA controller to perform the checkpointing process; and allocating memory storing operations corresponding to at least two of the multiple sections of the execution state to different channels of the multi-channel DMA controller.

6 . The method of claim 1 , comprising
in response to a power-restore signal, triggering the data processing circuitry to resume processing from an execution restart address, wherein the execution restart address comprises one of a plurality of possible execution restart addresses, each corresponding to completing storing of a different section of the execution state to the non-volatile memory.

7 . The method of claim 6 , comprising
storing the execution restart address in the non-volatile memory during the checkpointing process.

8 . The method of claim 7 , comprising
updating the execution restart address in the non-volatile memory following completion of storing of each of at least two of the multiple sections of the execution state to the non-volatile memory.

9 . The method of claim 6 , wherein
the checkpoint-progress status comprises the execution restart address.

10 . The method of claim 6 , comprising
determining the execution restart address by looking up an entry of a lookup table based on the checkpoint-progress status.

11 . The method of claim 1 , comprising
determining, based on the checkpoint-progress status, whether storing of one or more of the multiple sections of the execution state can be omitted from a further checkpointing process performed in response to a further power-drop warning.

12 . The method of claim 1 , comprising:
in response to a power-restore signal, performing a checkpoint-restore process comprising restoring the sections of the execution state that have been stored as part of the checkpointing process; and recording which of the restored sections are updated by the processing circuitry after performing the checkpoint-restore process.

13 . The method of claim 12 , comprising:
in response to a further power-drop warning received after the performing the checkpoint-restore process, performing a further checkpointing process; and during the further checkpointing process, omitting storing sections of the execution state that where stored during the checkpointing process and not updated by the data processing circuitry following the checkpoint-restore process.

14 . The method of claim 1 , wherein
the method is performed on an intermittent computing device.

15 . The method of claim 1 , wherein
the method is performed on a device powered by energy harvested by the device.

16 . A computer program which, when executed on a computer, causes the computer to perform the method of claim 1 .

17 . A storage medium storing the computer program of claim 16 .

18 . An apparatus for intermittent computing, the apparatus comprising:
data processing circuitry to perform data processing operations; and checkpointing circuitry to perform, in response to a power-drop warning, a checkpointing process comprising storing, to a non-volatile memory, execution state associated with the data processing operations performed by the data processing circuitry, wherein the checkpointing circuitry is configured to maintain, in the non-volatile memory, a checkpoint-progress status to indicate which of multiple sections of the execution state have been stored as part of the checkpointing process.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Garcia Redondo Fernando
• Švedas Jonas
• Gamage Sahan Sajeewa Hiniduma Udugama

Classifications

• G06F11/1407 Primary

  Checkpointing the instruction stream · CPC title

• G06F11/1438

  Restarting or rejuvenating · CPC title

• G06F1/30 Primary

  Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations (for resetting only G06F1/24) · CPC title

• G06F13/28

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F1/305 Primary

  in the event of power-supply fluctuations · CPC title