Memory integrity check

Patent metadata

Field	Value
Publication number	US-2023359523-A1
Application number	US-202318305497-A
Country	US
Kind code	A1
Filing date	Apr 24, 2023
Priority date	May 5, 2022
Publication date	Nov 9, 2023
Grant date	—

Abstract

A data processing device including a memory having a plurality of memory locations for respectively storing a value, wherein the data processing device has, for each memory location, an associated error detection memory area, a memory controller which is configured, when a value is written to a memory location, to store an associated error detection code in the error detection memory area associated with the memory location, a memory access element, and an integrity checker configured to perform an EDC check.

First claim

1 . A data processing device, comprising:
a memory having a plurality of memory locations each for storing a value; an associated error detection memory area for each memory location; a memory controller which is configured to store an associated error detection code in the error detection memory area associated with the memory location when a value is written to the memory location; a memory access element; and an integrity checker which is configured to store a reference value for a check function over values stored in the memory locations, representing the values stored in the memory locations, and after storing the reference value, to generate a check value for the check function by reading out the memory locations, and, starting from an initial value, updating the check value for each memory location read out with the value read from the memory location so that the check value represents the value, and, after generating the check value, comparing the reference value and the check value and outputting a first signal depending on a result of the comparison, wherein the integrity checker is configured to check, during a write access to a memory location, the error detection code stored before the write access in the error detection memory area belonging to the memory location to be written, and to output a second signal depending on the check.

2 . The data processing device as claimed in claim 1 , wherein the integrity checker is configured to repeatedly perform the generation of the check value and the comparison of the reference value with the check value.

3 . The data processing device as claimed in claim 2 , wherein the integrity checker is configured to perform the generation of the check value and the comparison of the reference value with the check value continuously or periodically.

4 . The data processing device as claimed in claim 1 , wherein the error detection code depends on the value stored in the memory location.

5 . The data processing device as claimed in claim 1 , wherein each memory location is identified by an address and the error detection code is obtained by applying an encoding function to at least the address identifying the memory location.

6 . The data processing device as claimed claim 1 , wherein the integrity checker is configured to check the error detection code which is stored in the error detection memory area associated with the memory location upon a read access to a memory location, and to output a third signal depending on the check.

7 . The data processing device as claimed in claim 1 , wherein the first signal indicates that one of the stored values has changed without write access by the memory access element or has not changed despite write access by the memory access element to change it.

8 . The data processing device as claimed in claim 1 , wherein the check function is a commutative operation of a mapping of the stored values.

9 . The data processing device as claimed in claim 1 , wherein the memory access element is a data processor that accesses the memory, wherein the memory is a non-volatile memory, a random access memory, or one or more registers.

10 . The data processing device as claimed in claim 1 , wherein the integrity checker is configured to output the first signal when the reference value does not match the check value.

11 . The data processing device as claimed in claim 5 , wherein the error detection code results from applying the encoding function to at least the value and address which identifies the memory location.

12 . A method for checking an integrity of a memory, comprising:
storing, when writing a value in a memory having a plurality of memory locations for storing a respective value, wherein each memory location has a respective error detection memory area associated therewith, an associated error detection code in the error detection memory area associated with the memory location; and storing a reference value for a check function over values stored in the memory locations which represent the values stored in the memory locations, and after storing the reference value, generating a check value for the check function by reading the memory locations and, starting from an initial value, updating the check value for each memory location read with the value read from the memory location, so that the check value represents the value, and comparing, after generating the check value, the reference value and the check value and outputting, depending on a result of the comparison, a first signal, wherein during a write access to a memory location, the error detection code which before the write access is stored in the error detection area belonging to the memory location to be written is checked, and a second signal is output depending on the check.

Assignees

• Infineon Technologies Ag

Inventors

• Sonnekalb Steffen

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F11/1004 Primary

  to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00) · CPC title