Dynamic load balancing of compute assets among different compute contexts

Patent metadata

Field	Value
Publication number	US-2023359499-A1
Application number	US-202318195230-A
Country	US
Kind code	A1
Filing date	May 9, 2023
Priority date	Mar 27, 2019
Publication date	Nov 9, 2023
Grant date	—

Abstract

Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

First claim

1 - 20 . (canceled)

21 . An apparatus comprising:
a graphics processing unit (GPU) including a plurality of processing resources and circuitry to dispatch at least one command for execution by the GPU, wherein the circuitry is to:
based on a configuration, permit execution of a first command of the at least one command by one or more particular processing resources of the GPU based on a source of the first command, wherein the configuration is to indicate one or more particular processing resources of the GPU permitted to execute commands from one or more particular sources.

22 . The apparatus of claim 21 , wherein in response to receipt of a second command from a second source while the first command is executing, the circuitry is to:
based on the configuration indicating that the second source is permitted to execute a command on the one or more particular processing resources that execute the first command: permit the first command to complete execution on the one or more particular processing resources and allocate the second command for execution on one or more particular processing resources that previously executed the first command.

23 . The apparatus of claim 22 , wherein the circuitry is to:
after completion of the first command, flush a write data buffer to a cache and invalidate state and constant caches associated with the one or more particular processing resources that executed the first command.

24 . The apparatus of claim 22 , wherein the circuitry is to:
in response to detection of completion of the second command and an unexecuted command from the source of the first command, allocate one or more of the processing resources formerly allocated to execute the second command to perform the unexecuted command from the second source.

25 . The apparatus of claim 22 , wherein the first command is associated with a compute context or a render context and based on completion of execution of the first command, permit access to the compute context or the render context for use by the second command.

26 . The apparatus of claim 21 , wherein the circuitry is to:
in response to receipt of a third command associated with a third source, allocate one or more of the processing resources to perform the third command based on the configuration.

27 . The apparatus of claim 21 , comprising a memory device communicatively coupled to the circuitry to dispatch at least one command for execution by the GPU, wherein the memory device is to store the configuration.

28 . The apparatus of claim 21 , comprising one or more of: a general purpose graphics processing unit or a central processing unit, wherein the general purpose graphics processing unit or the central processing unit is to execute a process that is a source of the first command.

29 . A method comprising:
dispatching a first command for execution by a first set of one or more processing resources of a graphics processing unit (GPU) based on a first configuration that indicates the first set of one or more particular processing resources of the GPU that are permitted to execute commands from one or more particular sources.

30 . The method of claim 29 , wherein the first command is associated with a first source and comprising:
based on a second configuration that indicates a second set of one or more particular processing resources of the GPU permitted to perform operations for the one or more particular sources of the first command, dispatching a second command to the second set of one or more particular processing resources of the GPU, wherein the second set of one or more particular processing resources of the GPU is at least partially different than the first set of one or more particular processing resources of the GPU, and wherein the second command is provided by the one or more particular sources of the first command.

31 . The method of claim 29 , comprising:
after completion of the first command, flushing a write data buffer to a cache and invalidating state and constant caches associated with the one or more particular processing resources that executed the first command.

32 . The method of claim 29 , comprising:
in response to receipt of a third command from a second source while the first command is executing: based on the first configuration indicating that the second source is permitted to execute a command on the one or more particular processing resources that execute the first command:
permitting the first command to complete execution on the first set of one or more particular processing resources,
allocating the third command for execution on one or more particular processing resources that previously executed the first command, and
in response to completion of the third command and an unexecuted command from the one or more particular sources of the first command, based on the first configuration, allocating one or more of the particular processing resources formerly allocated to execute the third command to perform the unexecuted command from the second source.

33 . The method of claim 30 , wherein the first command is associated with a compute context or a render context and based on completion of execution of the first command, permitting access to the compute context or the render context for use by the second command.

34 . The method of claim 32 , comprising:
in response to receipt of a fourth command associated with a third source, allocating one or more of the particular processing resources to perform the fourth command based on the first configuration.

35 . At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
dispatch a first command for execution by a first set of one or more processing resources of a graphics processing unit (GPU) based on a first configuration that indicates the first set of one or more particular processing resources of the GPU are restricted to execute commands from one or more particular sources.

36 . The non-transitory computer-readable medium of claim 35 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
based on a second configuration that indicates a second set of one or more particular processing resources of the GPU restricted to perform operations for the one or more particular sources of the first command, dispatch a second command to the second set of one or more particular processing resources of the GPU, wherein the second set of one or more particular processing resources of the GPU is at least partially different than the first set of one or more particular processing resources of the GPU, and wherein the second command is provided by the one or more particular sources of the first command.

37 . The non-transitory computer-readable medium of claim 35 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
after completion of the first command, flush a write data buffer to a cache and invalidate state and constant caches associated with the one or more particular processing resources that executed the first command.

38 . The non-transitory computer-readable medium of claim 35 , comprising instructions stored thereon, that if executed by one or more processors, cause the one or more processors to:
in response to receipt of a third command from a second source while the first command is executing:
based on the firs

Assignees

• Intel Corp

Inventors

• Valerio James
• Ranganathan Vasanth
• Ray Joydeep
• Kulkarni Rahul A
• Appu Abhishek R
• Boles Jeffery S
• Nalluri Hema C

Classifications

• G06F9/3887

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title

• G06F9/3888

  controlled by a single instruction for multiple threads [SIMT] in parallel · CPC title

• G06F9/3851

  from multiple instruction streams, e.g. multistreaming · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/5038 Primary

  considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration (scheduling strategies G06F9/4881 and subgroups) · CPC title