Vertical shielded gate accumulation field effect transistor

Patent metadata

Field	Value
Publication number	US-2023352577-A1
Application number	US-202318171029-A
Country	US
Kind code	A1
Filing date	Feb 17, 2023
Priority date	Apr 4, 2022
Publication date	Nov 2, 2023
Grant date	—

Abstract

An accumulation MOSFET includes a plurality of device cells. Each device cell includes a mesa adjoining a vertical trench is disposed in a doped semiconductor substrate. The mesa has a top mesa portion disposed on a bottom mesa portion. The top mesa portion has a width that is narrower than a width of the bottom mesa portion. The vertical trench adjoining the mesa has a top trench portion and a bottom trench portion. The top trench portion has a width that is wider than a width of the bottom trench portion. A dielectric is disposed on a sidewall of the vertical trench. A gate electrode disposed in the top trench portion forms an accumulation channel region in the top mesa portion and a shield electrode disposed in the bottom trench portion forms a depletion drift region in the bottom mesa portion.

First claim

What is claimed is:

1 . An accumulation MOSFET including a plurality of device cells, each device cell comprising:
a mesa disposed adjoining a vertical trench in a doped semiconductor substrate, the mesa having a top mesa portion disposed on a bottom mesa portion, the top mesa portion having a width that is narrower than a width of the bottom mesa portion, the vertical trench having a top trench portion adjoining the top mesa portion and a bottom trench portion adjoining the bottom mesa portion, the top trench portion having a width that is wider than a width of the bottom trench portion; a dielectric disposed on a sidewall of the vertical trench; a gate electrode disposed in the top trench portion, the gate electrode being configured to form an accumulation channel region in the top mesa portion across the dielectric disposed on the sidewall of the mesa; and a shield electrode disposed in the bottom trench portion, the shield electrode being configured to form a depletion drift region in the bottom mesa portion across the dielectric disposed on the sidewall of the mesa.

2 . The accumulation MOSFET of claim 1 , further comprising:
a N+ doped source region disposed above the accumulation channel region in the top mesa portion; and a N+ doped drain region disposed below the depletion drift region in the bottom mesa portion.

3 . The accumulation MOSFET of claim 1 , wherein the accumulation channel region is doped with n-type dopants in a range of about 1×10 +14 to 5×10 +16 atoms/cm 3 and the depletion drift region is doped with n-type dopants in a range of about 5×10 +16 atoms/cm 3 to 1×10 +18 atoms/cm 3 .

4 . The accumulation MOSFET of claim 1 , further comprising a N+ doped source region disposed above the accumulation channel region in the top mesa portion and a N+ doped drain region disposed below the depletion drift region in the bottom mesa portion.

5 . The accumulation MOSFET of claim 1 , wherein a gate-to-source voltage, Vgs=0 V, fully pinches off the accumulation MOSFET.

6 . The accumulation MOSFET of claim 1 , wherein the gate electrode has a work function greater than 5.0 eV.

7 . The accumulation MOSFET of claim 6 , wherein the gate electrode is made of P+ doped poly silicon, or a metal including copper, iron, platinum, palladium, or nickel.

8 . The accumulation MOSFET of claim 1 , wherein the gate electrode has a work function that is greater than a work function the shield electrode.

9 . The accumulation MOSFET of claim 1 , wherein each device cell is laid out in a stripe structure with a stripe width between 500 nm and 1000 nm, and the top mesa portion has a width between about 40 nm and 100 nm.

10 . The accumulation MOSFET of claim 1 , wherein each device cell is laid out in a stripe structure, wherein the mesa is a linear mesa, and the accumulation MOSFET further includes a p-dopant region disposed at an end of the linear mesa.

11 . The accumulation MOSFET of claim 1 , wherein each device cell has a columnar structure, and the gate electrode is disposed in a gate-all-around configuration around the top mesa portion.

12 . The accumulation MOSFET of claim 1 , wherein the plurality of device cells is disposed in an array in an area, and the accumulation MOSFET further includes a p-doped ring disposed on a periphery of the area.

13 . The accumulation MOSFET of claim 1 , wherein the dielectric disposed on a sidewall of the top trench portion includes a high-k dielectric, or a stack of layers of silicon dioxide (SiO 2 ) interface oxide and layers of a high-k dielectric.

14 . The accumulation MOSFET of claim 1 , wherein the shield electrode disposed in the bottom trench portion extends through the gate electrode disposed in the top trench portion to a top surface of the accumulation MOSFET, and the shield electrode and the gate electrode are isolated from each other by an inter-poly dielectric (IPD) layer.

15 . An accumulation metal-oxide-semiconductor field-effect transistor (MOSFET), comprising:
a mesa formed between a pair of vertical trenches in a semiconductor substrate, the mesa having a top mesa portion disposed on a bottom mesa portion, the top mesa portion having a width that is narrower than a width of the bottom mesa portion, the mesa including an accumulation channel region and a drift region; a source region disposed in the mesa; a dielectric disposed on a sidewall of mesa; a gate electrode disposed in the pair of vertical trenches, the gate electrode being biased to form the accumulation channel region in the top mesa portion across the dielectric disposed on the sidewall of the mesa; a super-junction structure including a n-doped column and a p-doped column disposed on the semiconductor substrate; and a current redistribution layer disposed between the mesa and the super-junction structure.

16 . The accumulation MOSFET of claim 15 , wherein the top mesa portion has a width between 20 nm and 100 nm.

17 . The accumulation MOSFET of claim 15 , wherein the gate electrode has a work function greater than 5.0 eV.

18 . The accumulation MOSFET of claim 15 , wherein a gate-to-source voltage, Vgs=0 V, fully pinches off the accumulation MOSFET.

19 . The accumulation MOSFET of claim 15 , wherein the current redistribution layer is formed in a n-type doped epitaxial layer disposed on the semiconductor substrate.

20 . A method for fabricating an accumulation MOSFET, the method comprising:
forming a mesa adjoining a vertical trench in a doped semiconductor substrate, the mesa having a top mesa portion disposed on a bottom mesa portion, the top mesa portion having a width that is narrower than a width of the bottom mesa portion, the vertical trench having a top trench portion adjoining the top mesa portion and a bottom trench portion adjoining the bottom mesa portion, the top trench portion having a width that is wider than a width of the bottom trench portion; disposing a dielectric on a sidewall of the vertical trench; disposing a gate electrode in the top trench portion; the gate electrode configured to form an accumulation channel region in the top mesa portion across the dielectric disposed on the sidewall of the mesa; and disposing a shield electrode in the bottom trench portion, the shield electrode configured to form a depletion drift region in the bottom mesa portion across the dielectric disposed on the sidewall of the mesa.

21 . The method of claim 20 , wherein the accumulation channel region in the top mesa portion is doped with n-type dopants in a range of about 1×10 +14 to 5×10 +16 atoms/cm 3 and the depletion drift region is doped with n-type dopants in a range of about 5×10 +16 atoms/cm 3 to 1×10 +18 atoms/cm 3 .

22 . The method of claim 20 , wherein the gate electrode and the shield electrode each have a work function that is greater than 5.0 eV.

23 . The method of claim 20 , wherein a gate-to-source voltage, Vgs=0 V, fully pinches off the accumulation MOSFET.

24 . The method of claim 20 , wherein the gate electrode is made of P+ doped poly silicon, or a metal including copper, iron, platinum, palladium, or nickel.

25 . The method of claim 20 , wherein the top mesa portion has a width between 20 nm and 100 nm.

Assignees

• Semiconductor Components Ind Llc

Inventors

• Moens Peter
• Padmanabhan Balaji
• Probst Dean E
• Venkatraman Prasad
• Sarkar Tirthajyoti
• Loechelt Gary Horst

Classifications

• H10D62/052

  by forming stacked epitaxial layers · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/0297

  using recessing of the gate electrodes, e.g. to form trench gate electrodes · CPC title

• H10D64/117

  Recessed field plates, e.g. trench field plates or buried field plates · CPC title

• H10D30/668 Primary

  having trench gate electrodes, e.g. UMOS transistors · CPC title