Uniform layouts for sram and register file bit cells

Patent metadata

Field	Value
Publication number	US-2023328947-A1
Application number	US-202318209988-A
Country	US
Kind code	A1
Filing date	Jun 14, 2023
Priority date	Jun 22, 2017
Publication date	Oct 12, 2023
Grant date	—

Abstract

Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

First claim

What is claimed is:

1 . An integrated circuit structure, comprising:
a substrate; an eight transistor (8T) register file (RF) bit cell on the substrate, the 8T RF bit cell comprising:
first, second, third and fourth active regions parallel along a first direction of the substrate;
first and second gate lines over the first, second, third and fourth active regions, the first and second gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction; and
third and fourth gate lines over the first and second active region, but not over the third and fourth active regions, the third and fourth gate lines parallel along the second direction of the substrate.

2 . The integrated circuit structure of claim 1 , wherein the first active region is an N-type doped active region, and the second, third and fourth active regions are P-type doped active regions.

3 . The integrated circuit structure of claim 1 , wherein the first, second, third and fourth active regions are in first, second, third and fourth silicon fins, respectively.

4 . The integrated circuit structure of claim 1 , wherein the first gate line is discontinuous between the second and third active regions, and the second gate line is continuous between the second and third active regions.

5 . The integrated circuit structure of claim 1 , wherein the 8T RF bit cell has an L-shape.

6 . The integrated circuit structure of claim 1 , wherein individual ones of the first, second, third and fourth gate lines are spaced apart from one another by trench contact lines parallel along the second direction of the substrate.

7 . An integrated circuit structure, comprising:
a substrate; a ten transistor (10T) 2-read 1-write register file (RF) bit cell on the substrate, the 10T 2-read 1-write RF bit cell comprising:
first, second, third and fourth active regions parallel along a first direction of the substrate; and
first, second, third and fourth gate lines over the first, second, third and fourth active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction, wherein the first, third and fourth gate lines are discontinuous between the second and third active regions, and the second gate line is continuous between the second and third active regions.

8 . The integrated circuit structure of claim 7 , wherein the first active region is an N-type doped active region, and the second, third and fourth active regions are P-type doped active regions.

9 . The integrated circuit structure of claim 7 , wherein the first, second, third and fourth active regions are in first, second, third and fourth silicon fins, respectively.

10 . The integrated circuit structure of claim 7 , wherein individual ones of the first, second, third and fourth gate lines are spaced apart from one another by trench contact lines parallel along the second direction of the substrate.

11 . An integrated circuit structure, comprising:
a substrate; a ten transistor (10T) 2-read 1-write register file (RF) bit cell on the substrate, the 10T 2-read 1-write RF bit cell comprising:
first, second, third and fourth active regions parallel along a first direction of the substrate; and
first, second, third and fourth gate lines over the first, second, third and fourth active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction, wherein the first and fourth gate lines are discontinuous between the second and third active regions, and the second and third gate lines are continuous between the second and third active regions.

12 . The integrated circuit structure of claim 11 , wherein the first active region is an N-type doped active region, and the second, third and fourth active regions are P-type doped active regions.

13 . The integrated circuit structure of claim 11 , wherein the first, second, third and fourth active regions are in first, second, third and fourth silicon fins, respectively.

14 . The integrated circuit structure of claim 11 , wherein individual ones of the first, second, third and fourth gate lines are spaced apart from one another by trench contact lines parallel along the second direction of the substrate.

Assignees

• Intel Corp

Inventors

• Guo Zheng
• Ong Clifford L
• Karl Eric A
• Bohr Mark T

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10D84/853

  comprising FinFETs · CPC title

• H10D84/00

  Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers · CPC title

• H10D89/10 Primary

  Integrated device layouts · CPC title

• H10B10/12 Primary

  comprising a MOSFET load element · CPC title