Three terminal memory cells and method of making the same

Patent metadata

Field	Value
Publication number	US-2023320104-A1
Application number	US-202217657363-A
Country	US
Kind code	A1
Filing date	Mar 31, 2022
Priority date	Mar 31, 2022
Publication date	Oct 5, 2023
Grant date	—

Abstract

The disclosed subject matter relates generally to memory devices and a method of forming the same. More particularly, the present disclosure relates to three terminal resistive random-access (ReRAM) memory structures having two bottom electrodes and one top electrode. The present disclosure provides a structure including a first bottom electrode having an upper surface, a second bottom electrode having an upper surface, a switching layer on the upper surface of the first electrode and the upper surface of the second electrode, an oxygen enhancement layer on the switching layer, and a top electrode on the oxygen enhancement layer, the top electrode is positioned above the first bottom electrode and the second bottom electrode.

First claim

What is claimed is:

1 . A structure comprising:
a first bottom electrode having an upper surface; a second bottom electrode having an upper surface; a switching layer on the upper surface of the first electrode and the upper surface of the second electrode; an oxygen enhancement layer on the switching layer; and a top electrode on the oxygen enhancement layer, the top electrode is positioned over the first bottom electrode and the second bottom electrode.

2 . The structure of claim 1 , wherein the switching layer is surrounded by a perimeter, and the top electrode and the oxygen enhancement layer have the same perimeter as the perimeter of the switching layer.

3 . The structure of claim 2 , wherein the first bottom electrode and the second bottom electrode are positioned inside a border defined by the perimeter of the switching layer.

4 . The structure of claim 2 , wherein the switching layer is shared by the first bottom electrode and the second bottom electrode.

5 . The structure of claim 4 , further comprising a transistor, the transistor including a drain, the drain is connected to the top electrode.

6 . The structure of claim 5 , further comprising an interconnect via on the top electrode.

7 . The structure of claim 6 , wherein the drain is connected to the top electrode through the interconnect via.

8 . The structure of claim 5 , wherein the transistor includes a gate, and the gate is connected to a word line.

9 . The structure of claim 8 , further comprising a first dielectric region, the first dielectric region comprising a first conductive line and a second conductive line, wherein the first bottom electrode is on the first conductive line and the second bottom electrode is on the second conductive line.

10 . The structure of claim 9 , wherein the first conductive line is connected to a source line and the second conductive line is connected to a bit line.

11 . The structure of claim 10 , further comprising a dielectric liner that surrounds at least the respective perimeters of the switching layer, the oxygen enhancement layer, and the top electrode.

12 . The structure of claim 2 , wherein the oxygen enhancement layer includes gadolinium oxide.

13 . The structure of claim 12 , wherein the switching layer includes copper.

14 . The structure of claim 13 , wherein the first bottom electrode and the second bottom electrode include tantalum, titanium nitride, tantalum nitride, or a combination thereof.

15 . A method of forming a structure in a memory device, the method comprising:
forming a first bottom electrode having an upper surface; forming a second bottom electrode having an upper surface; forming a switching layer on the upper surface of the first electrode and the upper surface of the second electrode; forming an oxygen enhancement layer on the switching layer; and forming a top electrode on the oxygen enhancement layer, the top electrode being formed over the first bottom electrode and the second bottom electrode.

16 . The method of claim 15 , wherein the switching layer is formed with a perimeter, and the top electrode and the oxygen enhancement layer are formed with the same perimeter as the perimeter of the switching layer.

17 . The method of claim 16 , wherein the first bottom electrode and the second bottom electrode are positioned inside a border defined by the perimeter of the switching layer.

18 . The method of claim 17 , further comprising forming a transistor including a drain and a gate, wherein the drain is connected to the top electrode and the gate is connected to a word line.

19 . The method of claim 18 , further comprising:
forming a first dielectric region; and forming a first conductive line and a second conductive line in the first dielectric region, wherein the first bottom electrode is formed on the first conductive line and the second bottom electrode is formed on the second conductive line.

20 . The method of claim 19 , wherein the first conductive line is connected to a source line and the second conductive line is connected to a bit line.

Assignees

• Globalfoundries Sg Pte Ltd

Inventors

• Thong Jia Rui
• Sun Jianxun
• Toh Eng Huat
• Tan Juan Boon

Classifications

• H01L27/2436 Primary

  Electricity · mapped topic

• H01L45/1253

  Electricity · mapped topic

• H01L45/1608

  Electricity · mapped topic

• H10B63/30 Primary

  comprising selection components having three or more electrodes, e.g. transistors · CPC title

• H10N70/021

  Formation of switching materials, e.g. deposition of layers · CPC title