Antenna assisted reram formation

Patent metadata

Field	Value
Publication number	US-2023309421-A1
Application number	US-202318205208-A
Country	US
Kind code	A1
Filing date	Jun 2, 2023
Priority date	Jan 27, 2021
Publication date	Sep 28, 2023
Grant date	—

Abstract

A memory structure comprises a ReRAM module embedded in a substrate. An insulative layer is formed on the substrate. A first electrode is located on the insulative layer. The first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area. A second electrode is located on the insulative layer. The second electrode is proximately connected to a second end of the ReRAM module. The second electrode comprises a second surface area, a plasma-interacting component, and a resistive component. The resistive component is located between the plasma-interacting component and the ReRAM module. A ratio of the first surface area to the second surface area creates a voltage between the first electrode and second electrode when the first surface area and second surfaces area are exposed to an application of plasma. The voltage forms a conductive filament in the ReRAM module.

First claim

What is claimed is:

1 . A memory structure comprising:
a ReRAM module embedded in a substrate; an insulative layer on a surface of the substrate; a first electrode on a surface of the insulative layer, wherein the first electrode is proximately connected to a first end of the ReRAM module and comprises a first surface area; and a second electrode on the surface of the insulative layer, wherein the second electrode is proximately connected to a second end of the ReRAM module and comprises:
a second surface area that is different than the first surface area.

2 . The memory structure of claim 1 , wherein the second electrode further comprises a plasma-interacting component on the surface of the insulative layer.

3 . The memory structure of claim 2 , wherein the second electrode further comprises a resistive component located on the surface of the insulative layer between the plasma-interacting component and the ReRAM module.

4 . The memory structure of claim 1 , wherein a ratio of the first surface area to the second surface area creates a formation voltage between the first electrode and second electrode when the first surface area and second surface area are exposed to an application of plasma during formation of a conductive filament.

5 . The memory structure of claim 4 , wherein the conductive filament has a target resistance value.

6 . The memory structure of claim 5 , wherein the resistive component provides a first resistance between the first electrode and the second electrode, wherein the first resistance is less than or equal to the target resistance value.

7 . The memory structure of claim 1 , wherein the first electrode and second electrode are composed of a material that can be chemically etched off the insulative layer.

8 . The memory structure of claim 1 , wherein the first electrode is composed of a material that can be chemically etched off the insulative layer.

9 . The memory structure of claim 1 , wherein the second electrode is composed of a material that can be chemically etched off the insulative layer.

10 . The memory structure of claim 1 , wherein at least one of the first end and the second end of the ReRAM module is connected to a memory-cell transistor in the memory structure.

Assignees

• IBM

Inventors

• Kim Youngseok
• Seo Soon-Cheon
• Ok Injo
• Reznicek Alexander

Classifications

• H10N70/011 Primary

  Manufacture or treatment of multistable switching devices · CPC title

• H10B63/20

  comprising selection components having two electrodes, e.g. diodes · CPC title

• H10N70/24

  based on migration or redistribution of ionic species, e.g. anions, vacancies · CPC title

• H10N70/257

  having switching assisted by radiation or particle beam, e.g. optically controlled devices · CPC title

• H10N70/841

  Electrodes · CPC title