Semiconductor device

Patent metadata

Field	Value
Publication number	US-2023262972-A1
Application number	US-202318190253-A
Country	US
Kind code	A1
Filing date	Mar 27, 2023
Priority date	Jun 8, 2020
Publication date	Aug 17, 2023
Grant date	—

Abstract

A semiconductor device includes a substrate including a first plate portion and a second plate portion, a stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, a first block separation structure on the first plate portion and a second block separation structure on the first plate portion. Each of the first and second block separation structures includes first separation regions, a cell array separation structure including a second separation region connected to the first separation regions and channel structures penetrating the stack structure, wherein the stack structure includes first stack structures separated by the first separation regions of the first block separation structure and extending in the first direction, second stack structures separated by the first separation regions of the second block separation structure, and at least one third stack structure separated from the first and second stack structures by the cell array separation structure.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
a first substrate including a first portion and a second portion spaced apart from the first portion; a first stack structure on the first portion; a second stack structure on the second portion and spaced apart from the first stack structure; at least one intermediate stack structure between the first stack structure and the second stack structure, and spaced apart from the first and second stack structures; first block separation structures penetrating through the first stack structure; second block separation structures penetrating through the second stack structure; a first intermediate separation structure between the at least one intermediate stack structure and the first stack structure; and a second intermediate separation structure between the at least one intermediate stack structure and the second stack structure, wherein each of the first and second stack structure includes interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, wherein the at least one intermediate stack structure includes first layers and second layers alternately stacked in the vertical direction, wherein each of the first and second block separation structures extends in a first direction parallel to an upper surface of the substrate, wherein each of the first and second intermediate separations extends in a second direction perpendicular to first direction, wherein a material of the first layers is the same material as a material of the interlayer insulating layers, and wherein an uppermost gate electrode of the gate electrodes is at a same level as an uppermost second layer of the second layers.

2 . The semiconductor device of claim 1 ,
wherein the uppermost gate electrode of the first stack structure contacts the first intermediate separation structure, and wherein the uppermost gate electrode of the second stack structure contacts the second intermediate separation structure.

3 . The semiconductor device of claim 1 ,
wherein the second layers include a material different from a material of the gate electrodes.

4 . The semiconductor device of claim 3 , further comprising a contact plug penetrating through the first layers and the second layers of the at least one intermediate stack structure.

5 . The semiconductor device of claim 4 , further comprising:
first channel structure penetrating through the first stack structure; and second channel structure penetrating through the second stack structure, wherein an upper surface of the contact plug is at a higher level than upper surfaces of the first and second channel structures.

6 . The semiconductor device of claim 5 ,
wherein the first channel structures are connected to the first portion, and wherein the second channel structures are connected to the second portion.

7 . The semiconductor device of claim 4 , wherein the first substrate further includes a third portion between the first portion and the second portion, and
wherein the third portion is spaced apart from the first and second portions.

8 . The semiconductor device of claim 4 , wherein the contact plug is connected to the third portion.

9 . The semiconductor device of claim 1 , further comprising:
a peripheral circuit region vertically overlapping the first stack structure, the second stack structure, and the at least one intermediate stack structure.

10 . The semiconductor device of claim 9 ,
wherein the peripheral circuit region includes a base substrate and a circuit device including a transistor.

11 . A semiconductor device, comprising:
a peripheral circuit region; and a memory cell region vertically overlapping the peripheral circuit region, wherein the memory cell region includes:
a first substrate including a first portion and a second portion spaced apart from the first portion;
first stack structures on the first portion;
second stack structures on the second portion and spaced apart from the first stack structure; and
at least one intermediate stack structure between the first stack structure and the second stack structure, and spaced apart from the first and second stack structures;
first channel structures penetrating through the first stack structures; and
second channel structures penetrating through the second stack structures,
wherein each of the first and second stack structures includes interlayer insulating layers and gate electrodes alternately stacked in a vertical direction, wherein the at least one intermediate stack structure includes first layers and second layers alternately stacked in the vertical direction, wherein a material of the first layers is the same material as a material of the interlayer insulating layers, and wherein an uppermost gate electrode of the gate electrodes is at a same level as an uppermost second layer of the second layers.

12 . The semiconductor device of claim 11 ,
wherein each of the first and second stack structures extends in a first horizontal direction, wherein the first stack structures are spaced apart from each other in a second horizontal direction perpendicular to the first horizontal direction, wherein the second stack structures are spaced apart from each other in the second horizontal direction, and wherein the at least one intermediate stack structure extends in the horizontal second direction.

13 . The semiconductor device of claim 11 , wherein the first substrate further includes a third portion between the first portion and the second portion,
wherein the third portion is spaced apart from the first and second portions, wherein each of the first, second, and third portion is a polysilicon layer, wherein the at least one intermediate stack structure vertically overlaps the third portion, and wherein each of the first, second and third portions includes a polysilicon layer.

14 . The semiconductor device of claim 11 ,
wherein the at least one intermediate stack structure includes:
a first intermediate stack structure spaced apart from the first and second stack structures;
a second intermediate stack structure between first intermediate stack structure and the first stack structures; and
a third intermediate stack structure between first intermediate stack structure and the second stack structures,
wherein the first intermediate stack structure includes the first layers and the second layers,
wherein each of the second and third intermediate stack structures includes third layers and fourth layers alternately stacked in the vertical direction,
wherein the third layers extend from the first layers,
wherein a material of the second layers is different from a material of the fourth layers, and
wherein the material of the fourth layers is at the same as a material of the gate electrodes.

15 . The semiconductor device of claim 11 , further comprising a contact plug penetrating through the first layers and the second layers of the at least one intermediate stack structure.

16 . The semiconductor device of claim 11 ,
wherein the memory cell region is on the peripheral circuit region.

17 . The semiconductor device of claim 11 ,
wherein the memory cell region is bonded to the peripheral circuit region.

18 . A semiconductor device, comprising:
a peripheral circuit region; and a memory cell region vertically overlapping the peripheral circuit region, wherein the memory cell region includes:
a first substrate including a first portion and a second portion spaced a

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jo Sangyoun
• Kanamori Kohji
• Jung Kwangyoung
• Han Jeehoon

Classifications

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W10/014

  using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• H10B41/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title