Methods and apparatus for forming backside power rails

Patent metadata

Field	Value
Publication number	US-2023260825-A1
Application number	US-202217670777-A
Country	US
Kind code	A1
Filing date	Feb 14, 2022
Priority date	Feb 14, 2022
Publication date	Aug 17, 2023
Grant date	—

Abstract

A method that forms a sacrificial fill material that can be selectively removed for forming a backside contact via for a transistor backside power rail. In some embodiments, the method may include performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

First claim

1 . A method for forming a sacrificial fill material, comprising:
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening; and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

2 . The method of claim 1 , wherein the sacrificial fill material is silicon, silicon germanium, silicon oxide, silicon nitride, silicon carbide, aluminum oxide, or hafnium oxide.

3 . The method of claim 2 , wherein the silicon or the silicon germanium contains a dopant of boron, phosphorous, carbon, oxygen, or antimony.

4 . The method of claim 2 , wherein the sacrificial fill material is SiGe 0.4 .

5 . The method of claim 1 , further comprising:
epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.

6 . The method of claim 5 , wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.

7 . The method of claim 1 performed in an integrated cluster tool without an air break or intermediate wet preclean process.

8 . The method of claim 1 , wherein the rate of the hydrogen chloride gas is approximately 70 sccm.

9 . The method of claim 1 performed in a process to form a backside power via for a transistor structure.

10 . The method of claim 1 , further comprising:
forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.

11 . A method of forming a backside power rail contact for a source/drain epitaxial (Epi) structure of a transistor, comprising:
forming an opening in a substrate; depositing a conformal layer of oxide on the substrate and in the opening; performing an etching process on the substrate and the opening, wherein the etching process is an anisotropic dry etch process using a chlorine gas to remove the conformal layer of oxide from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening; epitaxially growing a sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr; forming a source/drain Epi structure on the sacrificial fill material; forming a gate material on the source/drain Epi structure; forming at least one interconnect signal lines above the gate material; flipping the substrate to reveal a backside of the substrate; removing material of the substrate to expose the sacrificial fill material; selectively etching the sacrificial fill material to remove the sacrificial fill material; and forming the backside power rail contact which is self-aligned to the source/drain Epi structure.

12 . The method of claim 11 , wherein the sacrificial fill material is silicon germanium (SiGe).

13 . The method of claim 11 , further comprising:
epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material.

14 . The method of claim 13 , wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.

15 . The method of claim 11 , wherein the conformal layer of oxide is an aluminum oxide material.

16 . The method of claim 11 , wherein the rate of the hydrogen chloride gas is approximately 70 sccm.

17 . A non-transitory, computer readable medium having instructions stored thereon that, when executed, cause a method for forming a sacrificial fill material to be performed, the method comprising:
performing an etching process on a substrate with an opening that is conformally coated with an oxide layer, wherein the etching process is an anisotropic dry etch process using a chlorine gas that removes the oxide layer from a field of the substrate and only from a bottom portion of the opening, and wherein the etching process forms a partial oxide spacer in the opening and increases a depth of the opening; and epitaxially growing the sacrificial fill material in the opening by flowing a hydrogen chloride gas at a rate of approximately 60 sccm to approximately 90 sccm in a chamber pressure of approximately 1 Torr to approximately 100 Torr.

18 . The non-transitory, computer readable medium of claim 17 , the method further comprising:
epitaxially growing the sacrificial fill material using a selective epitaxial growth process with a selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material and wherein the selectivity of <100> crystal plane silicon material over <110> crystal plane silicon material is approximately 4:1 and greater.

19 . The non-transitory, computer readable medium of claim 17 , wherein the rate of the hydrogen chloride gas is approximately 70 sccm, wherein the method is performed in an integrated cluster tool without an air break or intermediate wet preclean process, or wherein the method is performed in a process to form a backside power via for a transistor structure.

20 . The non-transitory, computer readable medium of claim 17 , the method further comprising:
forming a self-aligned epitaxial source/drain structure of a transistor on the sacrificial fill material.

Assignees

• Applied Materials Inc

Inventors

• Ren He
• Lazkani Houssam
• Gaire Raman
• Naik Mehul
• Liu Kuan-Ting

Classifications

• H10W20/481

  on the rear surfaces of the wafers or substrates · CPC title

• H10W20/0696

  by using sacrificial placeholders, e.g. using sacrificial plugs · CPC title

• H10P90/124

  by processing the backside of the wafers · CPC title

• H10P14/20

  of semiconductor materials · CPC title

• H10W20/427

  Power or ground buses · CPC title