Row repair and accuracy improvements in analog compute-in-memory architectures

Patent metadata

Field	Value
Publication number	US-2023251943-A1
Application number	US-202318298906-A
Country	US
Kind code	A1
Filing date	Apr 11, 2023
Priority date	Apr 11, 2023
Publication date	Aug 10, 2023
Grant date	—

Abstract

Systems, apparatuses and methods may provide for technology that includes a plurality of analog to digital converters (ADCs), compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs. In one example, the technology uses a DAC disconnect scheme to statically bypass defective memory bitcells and compute capacitors to improve yield with minimal overhead, and dynamically boost the effective precision of the ADC in the presence of weight/activation sparsity in neural network (NN) compute.

First claim

We claim:

1 . A computing system comprising:
a network controller; and a processor coupled to the network controller, the processor including one or more substrates and logic coupled to the one or more substrates, the logic including:
a plurality of analog to digital converters (ADCs),
compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs, and
a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs.

2 . The computing system of claim 1 , wherein the logic further includes a controller to:
detect a defect in the CiM MAC hardware, disconnect an affected DAC in the plurality of DACs, wherein the affected DAC is associated with a row corresponding to the defect, activate at least one of the one or more redundant DACs, and remap inputs of the affected DAC to the at least one of the one or more redundant DACs.

3 . The computing system of claim 2 , wherein the logic further includes a plurality of switches, and wherein the affected DAC is disconnected via one or more of the plurality of switches.

4 . The computing system of claim 3 , wherein the plurality of switches are positioned between capacitors in the CiM MAC hardware and the plurality of ADCs.

5 . The computing system of claim 1 , wherein the instructions, when executed, further cause the computing system to:
detect one or more zero-valued input activations, disconnect one or more DACs corresponding to the one or more zero-valued input activations, and modify a scaling factor associated with the plurality of ADCs based on a number of the one or more DACs corresponding to the one or more zero-valued input activations.

6 . An apparatus comprising:
one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic including: a plurality of analog to digital converters (ADCs); compute-in-memory (CiM) multiply-accumulate (MAC) hardware coupled to the plurality of ADCs; and a plurality of digital to analog converters (DACs) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs.

7 . The apparatus of claim 6 , wherein the logic further includes a controller to:
detect a defect in the CiM MAC hardware; disconnect an affected DAC in the plurality of DACs, wherein the affected DAC is associated with a row corresponding to the defect; activate at least one of the one or more redundant DACs; and remap inputs of the affected DAC to the at least one of the one or more redundant DACs.

8 . The apparatus of claim 7 , wherein the logic further includes a plurality of switches, and wherein the affected DAC is disconnected via one or more of the plurality of switches.

9 . The apparatus of claim 8 , wherein the plurality of switches are positioned between capacitors in the CiM MAC hardware and the plurality of ADCs.

10 . The apparatus of claim 7 , wherein the controller is further to:
detect one or more zero-valued input activations; disconnect one or more DACs corresponding to the one or more zero-valued input activations; and modify a scaling factor associated with the plurality of ADCs based on a number of the one or more DACs corresponding to the one or more zero-valued input activations.

11 . The apparatus of claim 7 , wherein the defect is detected with respect to a bitcell in the MAC hardware.

12 . The apparatus of claim 7 , wherein the defect is detected with respect to a capacitance in the MAC hardware.

13 . The apparatus of claim 6 , wherein the logic coupled to the one or more substrates includes transistor regions that are positioned within the one or more substrates.

14 . At least one computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to:
detect a defect in compute-in-memory (CiM) multiply-accumulate (MAC) hardware, wherein the CiM MAC hardware is coupled to a plurality of analog to digital converters (ADCs) and a plurality of digital to analog converters (DACs), and wherein the plurality of DACs includes one or more redundant DACs; disconnect an affected DAC in the plurality of DACs, wherein the affected DAC is associated with a row corresponding to the defect; activate at least one of the one or more redundant DACs; and remap inputs of the affected DAC to the at least one of the one or more redundant DACs.

15 . The at least one computer readable storage medium of claim 14 , wherein the affected DAC is disconnected via one or more of a plurality of switches.

16 . The at least one computer readable storage medium of claim 15 , wherein the plurality of switches are to be positioned between capacitors in the CiM MAC hardware and the plurality of ADCs.

17 . The at least one computer readable storage medium of claim 14 , wherein the instructions, when executed, further cause the computing system to:
detect one or more zero-valued input activations; and disconnect one or more DACs corresponding to the one or more zero-valued input activations.

18 . The at least one computer readable storage medium of claim 17 , wherein the instructions, when executed, further cause the computing system to modify a scaling factor associated with the plurality of ADCs based on a number of the one or more DACs corresponding to the one or more zero-valued input activations.

19 . The at least one computer readable storage medium of claim 14 , wherein the defect is detected with respect to a bitcell in the CiM MAC hardware.

20 . The at least one computer readable storage medium of claim 14 , wherein the defect is detected with respect to a capacitance in the CiM MAC hardware.

Assignees

• Intel Corp

Inventors

• Dorrance Richard
• Liu Renzhi
• Wang Hechen
• Dasalukunte Deepak
• Carlton Brent

Classifications

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C29/702 Primary

  by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones · CPC title

• G06F11/2041 Primary

  with more than one idle spare processing component · CPC title