Vertical contacts for semiconductor devices

Patent metadata

Field	Value
Publication number	US-2023240067-A1
Application number	US-202318131097-A
Country	US
Kind code	A1
Filing date	Apr 5, 2023
Priority date	Mar 2, 2021
Publication date	Jul 27, 2023
Grant date	—

Abstract

Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

First claim

What is claimed is:

1 . A memory device having an array of vertically stacked memory cells with vertical contacts, the memory device comprising:
a substrate including circuitry components; a vertical stack of layers disposed on the substrate; horizontal conductive lines located along a horizontal plane in at least one layer of the vertical stack of layers; and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

2 . The memory device of claim 1 , wherein the group of layers comprises:
a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer.

3 . The memory device of claim 2 , wherein the horizontal conductive lines are located in the second dielectric material layer.

4 . The memory device of claim 1 , wherein the vertical contacts are formed of a conductive material.

5 . The memory device of claim 1 , wherein the vertical contacts directly electrically coupled to the horizontal conductive lines to the circuitry components in the absence of an additional interconnect.

6 . The memory device of claim 1 , wherein an electrical path between the horizontal conductive lines that are directly electrically coupled to the circuitry components is shorter than a comparative electrical path of a different memory device which employs at least an additional horizontal interconnect located between the horizontal conductive lines and the circuitry components.

7 . The memory device of claim 1 , further comprising an insulating material adjacent to at least a portion of the vertical contacts.

8 . The memory device of claim 7 , wherein the insulating material is selected from silicon oxide material, a silicon nitride material, a silicon oxynitride, or any combination thereof.

9 . The memory device of claim 1 , wherein the horizontal conductive lines are digit lines.

10 . The memory device of claim 1 , wherein the memory device is a three-dimensional (3D) dynamic random access memory device.

11 . The memory device of claim 1 , wherein the horizontal conductive lines are configured in a staircase contact structure.

12 . The memory device of claim 1 , wherein the array of vertically stacked memory cells further comprises a number of horizontal access devices.

13 . The memory device of claim 12 , wherein each horizontal access device of the number of horizontal access devices is directly electrically coupled, via a respective vertical contact of the vertical contacts, to a corresponding circuitry component.

14 . The memory device of claim 13 , wherein a total number of the vertical contacts is equal to a total number of the number of horizontal access devices.

15 . A method for forming an array of vertically stacked memory cells, having vertical contacts, the method comprising:
forming a number of layers, in repeating iterations vertically to form a vertical stack on a substrate, the layers comprising a dielectric material layer having multi-direction horizontal conductive lines formed along a horizontal plane therein; the multi-direction horizontal conductive lines each having a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction; performing a removal process to form a staircase contact structure, forming spaced, vertical openings through the vertical stack adjacent to each of the multi-direction horizontal conductive lines in the staircase contact structure; depositing an insulating material in the spaced, vertical openings; and depositing conductive material in the spaced, vertical openings to form vertical contacts to directly electrically couple the multi-direction horizontal conductive lines in the staircase contact structure to a circuitry components in the substrate.

16 . The method of claim 15 , wherein forming the spaced, vertical openings further comprises forming the spaced, vertical openings through the vertical stack adjacent to the second portion of each of the multi-direction horizontal conductive lines in the staircase contact structure.

17 . The method of claim 15 , wherein forming the spaced, vertical openings further comprises forming the spaced vertical openings that extend at least along an entire respective distance between each of the multi-direction horizontal conductive lines and the substrate.

18 . A memory device having an array of vertically stacked memory cells, the memory device comprising:
a vertical stack of materials on a substrate, the vertical stack of materials comprising a dielectric material having multi-direction horizontal conductive lines located therein, wherein each of the multi-direction horizontal conductive lines has a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction and wherein the second portions are laterally spaced to allow for vertical contacts to be coupled to the second portions; and vertical contacts coupled to the second portions of the multi-directional horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of materials to directly electrically couple respective ones of the multi-directional horizontal conductive lines to a corresponding circuitry components located in the substrate.

19 . The memory device of claim 18 , wherein the multi-directional horizontal conductive lines are horizontal digit lines or horizontal word lines.

20 . The memory device of claim 19 , wherein the array of vertically stacked memory cells is electrically coupled in an open digit line architecture or a folded digit line architecture.

Assignees

• Micron Technology Inc

Inventors

• Kim Byung Yoon
• Hwang Sangmin
• Lee Kyuseok

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title