Vertical contacts for semiconductor devices

Patent metadata

Field	Value
Publication number	US-11631681-B2
Application number	US-202117189485-A
Country	US
Kind code	B2
Filing date	Mar 2, 2021
Priority date	Mar 2, 2021
Publication date	Apr 18, 2023
Grant date	Apr 18, 2023

Abstract

Embodiments herein relate to vertical contacts for semiconductor devices. For instance, a memory device having vertical contacts can comprise a substrate including circuitry components, a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer, and vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

First claim

What is claimed is:

1. A memory device having arrays of vertically stacked memory cells with vertical contacts, the memory device comprising:
a substrate including circuitry components;
a vertical stack of layers formed from repeating iterations of a group of layers disposed on the substrate, the group of layers comprising:
a first dielectric material layer,
a semiconductor material layer, and
a second dielectric material layer including horizontal conductive lines formed along a horizontal plane in the second dielectric material layer; and

vertical contacts coupled to the horizontal conductive lines, the vertical contacts extending along a vertical plane within the vertical stack of layers to directly electrically couple the horizontal conductive lines to the circuitry components.

2. The memory device of claim 1 , wherein the vertical contacts are formed of a conductive material.

3. The memory device of claim 2 , wherein the vertical contacts are formed of a doped semiconductor material, a conductive metal nitride, a metal, a metal-semiconductor compound, or any combination thereof.

4. The memory device of claim 1 , wherein the vertical contacts are directly electrically coupled to the horizontal conductive lines to the circuitry components in the absence of an additional interconnect.

5. The memory device of claim 1 , wherein an electrical path between the horizontal conductive lines that are directly electrically coupled to the circuitry components is shorter than a comparative electrical path of a different memory device which employs at least an additional horizontal interconnect located between the horizontal conductive lines and the circuitry components.

6. The memory device of claim 1 , further comprising an insulating material adjacent to at least a portion of the vertical contacts.

7. The memory device of claim 6 , wherein the insulating material is selected from silicon oxide material, a silicon nitride material, a silicon oxynitride, or any combination thereof.

8. The memory device of claim 1 , wherein the horizontal conductive lines are digit lines.

9. The memory device of claim 1 , wherein the memory device is a three- dimensional (3D) dynamic random access memory device.

10. The memory device of claim 1 , wherein the horizontal conductive lines are configured in a staircase contact structure.

11. The memory device of claim 1 , wherein the arrays of vertically stacked memory cells further comprises a number of horizontal access devices.

12. The memory device of claim 11 , wherein each horizontal access device of the number of horizontal access devices is directly electrically coupled, via a respective vertical contact of the vertical contacts, to a corresponding circuitry component.

13. The memory device of claim 12 , wherein a total number of the vertical contacts is equal to a total number of the number of horizontal access devices.

14. A method for forming arrays of vertically stacked memory cells, having vertical contacts, comprising:
forming a number of layers, in repeating iterations vertically to form a vertical stack on a substrate, the layers comprising: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer having a conductive line formed along a horizontal plane therein; the second dielectric material layer having multiple multi-direction horizontal conductive lines has a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction and wherein the second portions are laterally spaced with respect to each other to allow for vertical contacts to be coupled to the second portions;
performing a removal process in repeating vertical iterations at an area that includes at least a section of the second portion of the conductive line to form a staircase contact structure, forming spaced, vertical openings through the vertical stack adjacent to each of the multiple multi-direction horizontal conductive lines in the staircase contact structure;
conformally depositing an insulating material in the spaced, vertical openings; and
depositing conductive material in the spaced, vertical openings to form vertical contact to directly electrically couple the multiple multi-direction horizontal conductive lines in the staircase contact structure to a circuitry components in the substrate.

15. The method of claim 14 , wherein forming the spaced, vertical openings further comprises forming the spaced, vertical openings through the vertical stack adjacent to the second portion of each of the multiple multi-direction horizontal conductive lines in the staircase contact structure.

16. The method of claim 14 , wherein forming the spaced, vertical openings further comprises forming the spaced vertical openings that extend at least along an entire respective distance between each of the multiple multi-direction horizontal conductive lines and the substrate.

17. The method of claim 14 , wherein performing the removal process to form the staircase contact structure comprises:
selectively removing a first portion of each layer of a first group of layers of the number of layers by removing the first portion of each layer of the first group of layers between a reference line and a first lateral distance from the reference line;
selectively removing a portion of each layer of a second group of layers of the number of layers by removing the portion of each layer of the second group of layers between the reference line and a second distance back from the reference line; and
selectively removing a second portion of each layer of the first group of layers of the number of layers by removing the second portion of each layer of the first group of layers between the reference line and a third distance back from the reference line and wherein the third distance is greater than the second distance.

18. A memory device comprising:
conductive circuitry contacts;
a plurality of stacked horizontal conductive lines with insulating layers interposed between each of the plurality of stacked horizontal conductive lines;
an insulating material disposed on the sidewalls of the insulating layers interposed between each of the horizontal conductive lines and on sidewalls of each of the stacked horizontal conductive lines; and
a plurality of vertical contacts coupled to respective top surfaces of the plurality of stacked horizontal conductive lines to directly electrically couple the respective top surfaces to a corresponding conductive circuitry contact of the conductive circuitry contacts.

19. The memory device of claim 18 , wherein the one or more horizontal conductive lines are horizontal digit lines or word lines.

20. The memory device of claim 18 , wherein the insulating material is conformally disposed an entirety of the sidewalls of the insulating layers and the sidewalls of each of the stacked conductive lines but is not disposed on the respective top surfaces of the plurality of stacked horizontal conductive lines.

Assignees

• Micron Technology Inc

Inventors

• Kim Byung Yoon
• Hwang Sangmin
• Lee Kyuseok

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title