Memory module with local synchronization and method of operation

Patent metadata

Field	Value
Publication number	US-2023236970-A1
Application number	US-202218059958-A
Country	US
Kind code	A1
Filing date	Nov 29, 2022
Priority date	Jul 27, 2013
Publication date	Jul 27, 2023
Grant date	—

Abstract

A memory module is operable in a computer system having a memory controller and a system bus and comprises memory devices organized in one or more ranks and in a plurality of groups, and circuits configurable to receive from the memory controller a system clock and input control and address (C/A) signals, generate a module clock signal and module C/A signals in response to the system clock and input C/A signals, generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, and output the plurality of local clock signals to respective groups of the memory devices. A respective local clock signal has a respective phase relationship with the module clock signal and is output to a corresponding group of the memory devices that includes at least one corresponding memory device in each of the one or more ranks.

First claim

we claim:

1 . A memory module operable in a computer system having a memory controller and a system bus, the system bus including one or more clock signal lines, a set of control/address (C/A) signal lines and a plurality of sets of data/strobe signal lines, the memory module comprising:
a printed circuit board (PCB) having connectors formed along an edge thereof for connecting to respective ones of the C/A signal lines and the plurality of sets of data/strobe signal lines; memory devices mounted on the PCB and organized in one or more ranks and in a plurality of groups, a respective group of the memory devices including at least one respective memory device in each of the one or more ranks and configured to communicate data/strobe signals with the memory controller via a respective set of the plurality of sets of data/strobe signal lines; circuits mounted on the PCB and configurable to:
receive from the memory controller a system clock via the one or more clock signal lines and input control and address (C/A) signals via the set of C/A signal lines;
generate a module clock signal and module C/A signals in response to the system clock and input C/A signals;
generate a plurality of local clock signals corresponding, respectively, to the plurality of groups of memory devices, the plurality of local clock signals having respective phase relationships with the module clock signal; and
output the module C/A signals to the memory devices, wherein the module C/A signals including one or more chip select signals corresponding, respectively, to the one or more ranks; and
output the plurality of local clock signals to respective groups of the memory devices, wherein a respective local clock signal having a respective programmable phase relationship with the module clock signal is output to a corresponding group of the memory devices, the corresponding group of the memory devices including at least one corresponding memory device that performs a memory read or write operation by communicating data/strobe signals with the memory controller via a corresponding set of the plurality of sets of data/strobe signal lines in accordance with the respective local clock signal and in response to module C/A signals received by the at least one corresponding memory device.

2 . The memory module of claim 1 , wherein the circuits include logic and configuration registers programmable by the logic to control the respective programmable phase relationships.

3 . The memory module of claim 2 , wherein:
the memory module is operable in at least a normal operation mode and a configuration mode; the memory module in the normal operation mode is configurable to output or receive data/strobe signals via the data/strobe signal lines in response to memory read or write commands received via the C/A signal lines; and the memory module in the configuration mode is configurable to perform a set of operations and the logic is further configurable to program the respective configuration registers based on information derived from the set of operations.

Assignees

• Netlist Inc

Inventors

• Lee Hyun
• Bhakta Jayesh R

Classifications

• G06F12/0802 Primary

  Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches · CPC title

• G11C5/04 Primary

  Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C7/1066

  Output synchronization · CPC title