Adjustable well capacity pixel for semiconductor imaging sensors

Patent metadata

Field	Value
Publication number	US-2023215885-A1
Application number	US-202117566603-A
Country	US
Kind code	A1
Filing date	Dec 30, 2021
Priority date	Dec 30, 2021
Publication date	Jul 6, 2023
Grant date	—

Abstract

An imaging pixel design is provide with a photo-sensor block structure that facilitates dynamic control of well capacity in the photodiode region (i.e., a “well capacity adjustment (WCA) gate photo-sensor block”). The photodiode region includes a doped well in which photocharge is accumulated responsive to exposure to incident illumination. The capacity of the well corresponds to a well potential. WCA structures (e.g., deep trench regions) form walls at least partially surrounding and capacitively coupling with the doped well, such that biasing of the WCA structures changes the well potential and the corresponding well capacity. As such, the WCA structures can be biased during integration to increase the well potential to a high level for large well capacity, and the WCA structures can be differently biased during photocharge transfer to decrease the well potential to a sufficiently low level that avoids lag and/or other conventional concerns.

First claim

What is claimed is:

1 . A method for selective photodiode well capacity adjustment in an imaging sensor pixel, the method comprising:
first configuring the WCA gate photo-sensor block to operate in an integration mode for an integration time window by:
setting a transfer gate of a well-capacity-adjustment (WCA) gate photo-sensor block to form a potential barrier between a photodiode region of the WCA gate photo-sensor block and a floating diffusion (FD) region of the WCA gate photo-sensor block, the photodiode region having a doped well implanted in a semiconductor substrate to have a well capacity defined at least by a well potential;
setting a WCA gate of the WCA gate photo-sensor block to a first biasing, the WCA gate integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well, such that the first biasing pushes the well potential to a first well potential that corresponds to a full well capacity; and
directing exposing the photodiode region to incident illumination to cause accumulation of photocharge in the doped well during the integration time widow;
second configuring the WCA gate photo-sensor block to operate in a transfer mode for a transfer time window subsequent to the integration time window by:
setting the transfer gate to form a current channel between the doped well and the FD region; and
setting the WCA gate to a second biasing to pull the well potential to a second well potential that corresponds to a reduced well capacity, the second well potential being less than a channel potential of the current channel, the channel potential being less than a FD potential of the FD region.

2 . The method of claim 1 , wherein the first well potential is greater than the channel potential.

3 . The method of claim 1 , wherein the first well potential is greater than the FD potential.

4 . The method of claim 1 , wherein the second configuring comprises performing the setting the transfer gate to form the current channel prior to setting the WCA gate to the second biasing.

5 . The method of claim 1 , wherein the second configuring causes the photocharge accumulated in the doped well during the integration time window to transfer to the FD region via the current channel as transferred photocharge, and further comprising:
third configuring the WCA gate photo-sensor block to operate in a spill-back suppression mode for a spill-back suppression time window subsequent to the transfer time window by re-setting the transfer gate to form the potential barrier between the doped well and the FD region while continuing the setting of the WCA gate to the second biasing.

6 . The method of claim 5 , further comprising:
fourth configuring the WCA gate photo-sensor block to operate in a readout mode for a readout time window subsequent to the spill-back suppression time window by directing readout of the transferred photocharge from the FD region by readout circuitry coupled with the FD region with the transfer gate set to form the potential barrier.

7 . The method of claim 6 , wherein the fourth configuring further comprises:
re-setting the WCA gate to the first biasing during the readout time window.

8 . A imaging sensor pixel comprising:
a well-capacity-adjustment (WCA) gate photo-sensor block configured selectively to operate in at least an integration mode and a transfer mode, the WCA gate photo-sensor block comprising:
a photodiode region having a doped well implanted into a semiconductor substrate to accumulate photocharge responsive to exposure of the WCA gate photo-sensor block to incident illumination, the doped well having a well capacity defined at least by a well potential;
a WCA gate integrated in the semiconductor substrate to form walls that at least partially surround and capacitively couple with the doped well, such that the well potential is based at least on biasing of the WCA gate;
a floating diffusion (FD) region implanted into the semiconductor substrate to have a FD potential; and
a transfer gate to selectively form a current channel between the doped well and the floating diffusion region, the current channel having a channel potential less than the FD potential,
wherein, in the integration mode, the WCA gate is first-biased to set the well potential to a first well potential corresponding to a full well capacity, and wherein, in the transfer mode, the WCA gate is second-biased to set the well potential to a second well potential that is less than the first well potential, is less than the channel potential, and corresponds to a reduced well capacity.

9 . The imaging sensor pixel of claim 8 , wherein the first well potential is greater than the channel potential.

10 . The imaging sensor pixel of claim 1 , wherein the first well potential is greater than the FD potential.

11 . The imaging sensor pixel of claim 8 , wherein:
the WCA gate photo-sensor block is configured selectively to operate further in a spill-back suppression mode; in the integration mode, the transfer gate is set to be OFF to form a potential barrier between the doped well and the floating diffusion region with the WCA gate set to be first-biased during accumulation of photocharge in the photodiode region; in the transfer mode, the transfer gate is set to be ON to form the current channel between the doped well and the floating diffusion region with the WCA gate set to be second-biased, such that accumulated photocharge transfers from the doped well to the floating diffusion region via the current channel as transferred photocharge; and in the spill-back suppression mode, the transfer gate is set to be OFF to form the potential barrier between the doped well and the floating diffusion region with the WCA gate set to be second-biased.

12 . The imaging sensor pixel of claim 11 , wherein:
the WCA gate photo-sensor block is configured selectively to operate further in a readout mode; in the readout mode, the transfer gate is set to be OFF to form the potential barrier between the doped well and the floating diffusion region with the WCA gate set to be first-biased during readout of the transferred photocharge from the floating diffusion region.

13 . The imaging sensor pixel of claim 8 , wherein:
the WCA gate comprises one or more WCA structures electrically coupled with a WCA terminal and forming the walls that at least partially surround and capacitively couple with the doped well, the WCA terminal configured to receive a biasing signal to bias the WCA structures.

14 . The imaging sensor pixel of claim 13 , wherein:
the one or more WCA structures comprise a single contiguous deep-trench structure that is integrated with the semiconductor substrate and forms the walls that at least partially surround and capacitively couple with the doped well.

15 . The imaging sensor pixel of claim 13 , wherein:
the one or more WCA structures comprise a plurality of deep-trench structures integrated with the semiconductor substrate, each of the deep-trench structures forming one or more of the walls that at least partially surround and capacitively couple with the doped well.

16 . The imaging sensor pixel of claim 8 , wherein:
the photodiode region is configured as a pinned photodiode, and the well potential is the pinning voltage of the pinned photodiode.

17 . A complementary metal-oxide semiconductor (CMOS) imaging sensor (CIS) comprising:
an array of imaging pixels, each imaging pixel comprising a well-capacity-adjustment (WCA) gate photo-sensor block, each WCA gate photo-se

Assignees

• Shenzhen Goodix Tech Co Ltd

Inventors

• Gao Yunfei
• Oh Tae Seok

Classifications

• H10F39/8037

  the integrated elements comprising a transistor · CPC title

• H10F39/803

  Pixels having integrated switching, control, storage or amplification elements · CPC title

• H10F39/802

  Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title

• H04N25/59

  by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance · CPC title

• H10F39/18 Primary

  Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors · CPC title