Microelectronic devices having air gap structures integrated with interconnect for reduced parasitic capacitances

Patent metadata

Field	Value
Publication number	US-2023207446-A1
Application number	US-202318170754-A
Country	US
Kind code	A1
Filing date	Feb 17, 2023
Priority date	Dec 30, 2016
Publication date	Jun 29, 2023
Grant date	—

Abstract

Embodiments of the invention include a microelectronic device that includes a substrate, at least one dielectric layer on the substrate and a plurality of conductive lines within the at least one dielectric layer. The microelectronic device also includes an air gap structure that is located below two or more of the plurality of conductive lines.

First claim

1 .- 7 . (canceled)

8 . A method of fabricating an interconnect structure, the comprising:
forming at least one dielectric layer and a conductive layer having a plurality of conductive lines within the at least one dielectric layer; and forming at least one air gap structure that is integrated with the interconnect structure, the at least one air gap structure is positioned between adjacent conductive lines of the plurality of conductive lines, wherein the at least one air gap structure comprises a group III Nitride layer formed on a region of the at least one air gap structure.

9 . The method of claim 8 , further comprising:
a metallization stack that includes first and second metal layers with the plurality of conductive lines being at the first metal layer of the metallization stack.

10 . The method of claim 8 , wherein the group III Nitride layer comprises an Aluminum Nitride layer, a Boron Nitride layer, a Gallium Nitride layer, an Indium Nitride layer, or any combination of these group III Nitride layers.

11 . The method of claim 8 , wherein the group III Nitride layer has a thickness of 50 to 250 nanometers.

12 . The method of claim 8 , wherein the interconnect structure is disposed on a substrate to form a microelectronic device.

13 . The method of claim 8 , wherein the region is an upper region and sidewalls of the at least one air gap structure.

14 . The method of claim 8 , wherein each air gap structure has a substantially rectangular shape or a substantially trapezoidal shape.

15 . A computing device, comprising:
a board; and a component coupled to the board, the component including an integrated circuit structure, comprising:
at least one dielectric layer and a conductive layer having a plurality of conductive lines within the at least one dielectric layer; and
at least one air gap structure that is integrated with the interconnect structure, the at least one air gap structure is positioned between adjacent conductive lines of the plurality of conductive lines, wherein the at least one air gap structure comprises a group III Nitride layer formed on a region of the at least one air gap structure.

16 . The computing device of claim 15 , further comprising:
a memory coupled to the board.

17 . The computing device of claim 15 , further comprising:
a communication chip coupled to the board.

18 . The computing device of claim 15 , further comprising:
a camera coupled to the board.

19 . The computing device of claim 15 , wherein the component is a packaged integrated circuit die.

20 . The computing device of claim 15 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.

Assignees

• Tahoe Res Ltd

Inventors

• Then Han Wui
• Dasgupta Sansaptak
• Radosavljevic Marko
• Gardner Sanaz K

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/47

  comprising two or more dielectric layers having different properties, e.g. different dielectric constants · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W10/021 Primary

  of air gaps · CPC title

• H10W10/20

  Air gaps · CPC title