High Resolution Attenuator or Phase Shifter with Weighted Bits

Patent metadata

Field	Value
Publication number	US-2023198491-A1
Application number	US-202218082360-A
Country	US
Kind code	A1
Filing date	Dec 15, 2022
Priority date	Jun 20, 2018
Publication date	Jun 22, 2023
Grant date	—

Abstract

Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.

First claim

1 . An electronic circuit, including:
(a) a transmission line coupled to multiple shunt signal-alteration stages, each signal-alteration stage being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in a signal-alteration state; (b) wherein each signal-alteration stage is configured with components to provide an associated value of signal alteration; and (c) wherein the associated value of signal alteration for a plurality of the signal-alteration stages is a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal alteration having a resolution finer than the signal alteration value of a lowest-valued signal-alteration stage.

2 . The invention of claim 1 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function.

3 . The invention of claim 1 , wherein the bit position weighting function is one of a geometric series function or an alternating geometric series function.

4 . The invention of claim 1 , wherein the bit position weighting function is one of a harmonic series function or an alternating harmonic series function.

5 . The invention of claim 1 , wherein the associated value of signal alteration for at least one stage is a fixed signal alteration value.

6 . The invention of claim 1 , further including at least one signal-alteration stage having a signal alteration value set to a value not determined by the bit position weighting function.

7 . The invention of claim 1 , wherein at least one of the at least one signal-alteration stage attenuates a signal applied to the transmission line.

8 . The invention of claim 1 , wherein at least one of the at least one signal-alteration stage alters a phase of a signal applied to the transmission line.

9 . An electronic transmission line digital step attenuator circuit, including:
(a) a transmission line coupled to multiple shunt attenuator stages, each stage including a resistance and being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in an attenuation state; (b) wherein each stage is configured with components to provide an associated value of signal attenuation; and (c) wherein the associated value of signal attenuation for a plurality of the stages is a function of a corresponding bit position weight determined by applying a bit position weighting function that produces intermediate steps of signal attenuation having a resolution finer than the signal attenuation value of a lowest-valued attenuator stage.

10 . The invention of claim 9 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function.

11 . The invention of claim 9 , wherein the bit position weighting function is one of a geometric series function or an alternating geometric series function.

12 . The invention of claim 9 , wherein the bit position weighting function is one of a harmonic series function or an alternating harmonic series function.

13 . The invention of claim 9 , wherein the associated value of signal attenuation for at least one stage is a fixed signal attenuation value.

14 . The invention of claim 9 , further including at least one attenuation stage having a signal attenuation value set to a value not determined by the bit position weighting function.

15 . An electronic transmission line digital phase shifter circuit, including:
(a) a transmission line coupled to multiple shunt phase shifter stages, each stage including a reactance and being assigned a bit position and being digitally selectable by an associated control line to be in a reference state or in a phase shift state; (b) wherein each stage is configured with components to provide an associated value of signal phase shift; and (c) wherein the associated value of signal phase shift for a plurality of the stages is a function of a corresponding bit position weight determined by applying a bit position weighting function.

16 . The invention of claim 15 , wherein the bit position weighting function is one of a linear series function or an alternating linear series function.

17 . The invention of claim 15 , wherein the bit position weighting function is one of a geometric series function or an alternating geometric series function.

18 . The invention of claim 15 , wherein the bit position weighting function is one of a harmonic series function or an alternating harmonic series function.

19 . The invention of claim 15 , wherein the associated value of signal phase shift for at least one stage is a fixed signal phase shift value.

20 . The invention of claim 15 , further including at least one phase shifter stage having a signal phase shift value set to a value not determined by the bit position weighting function.

Assignees

• Psemi Corp

Inventors

• Sharma Vikas
• Bacon Peter

Classifications

• H03H11/245

  using field-effect transistor · CPC title

• H03K17/687

  the devices being field-effect transistors · CPC title

• H03H7/20

  Two-port phase shifters providing an adjustable phase shift · CPC title

• H03H11/20

  Two-port phase shifters providing an adjustable phase shift · CPC title

• H03H7/25 Primary

  comprising an element controlled by an electric or magnetic variable (H03H7/27 takes precedence) · CPC title