Liquid metal interconnect for modular system on an interposer server architecture

Patent metadata

Field	Value
Publication number	US-2023197622-A1
Application number	US-202117559431-A
Country	US
Kind code	A1
Filing date	Dec 22, 2021
Priority date	Dec 22, 2021
Publication date	Jun 22, 2023
Grant date	—

Abstract

An electronic system and associated methods are disclosed. In one example, the electronic system includes an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a packaged companion IC to the processor IC attached to a second array surface of the second liquid metal well array.

First claim

1 . An electronic system, comprising:
an interposer including electrically conductive interposer interconnect, a first interposer surface, and a second interposer surface; a processor package including at least one processor integrated circuit (IC), the processor package attached to the first interposer surface and electrically connected to the interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to the second interposer surface and the interposer interconnect; a second liquid metal well array including a first array surface attached to the first interposer surface and the interposer interconnect; and a companion component package attached to a second array surface of the second liquid metal well array, wherein the companion component package includes a companion component to the processor IC.

2 . The electronic system of claim 1 , including:
a mother board including mother board interconnect; and wherein a pitch of the first liquid metal well array matches a pitch of the mother board interconnect and a pitch of the second liquid metal well array is a finer pitch than the pitch of the first liquid metal well array.

3 . The electronic system of claim 1 , wherein the liquid metal wells of the second liquid metal well array are attached to conductive pillars on the first interposer surface and to conductive pillars of the companion component package.

4 . The electronic system of claim 1 ,
wherein the second liquid metal well array includes solid metal contact pads on the first array surface attached to the first interposer surface using solder bumps; and wherein the liquid metal wells of the second liquid metal well array are attached to conductive pillars of the companion component package at the second array surface of the second liquid metal well array.

5 . The electronic system of claim 1 , wherein the companion component package includes a memory IC.

6 . The electronic system of claim 1 , wherein the companion component package includes a field programmable gate array (FPGA).

7 . The electronic system of claim 1 , wherein the companion component package includes a voltage regulator IC.

8 . The electronic system of claim 1 , wherein the companion component package includes at least one circuit component of a voltage regulator circuit.

9 . The electronic system of claim 1 , wherein the companion component package includes a circuit package that includes a high-speed input-output (HSIO) connector.

10 . The electronic system of claim 1 , including:
multiple liquid metal well arrays attached to the first interposer surface, wherein the multiple liquid metal well arrays attached to the first interposer surface have a finer pitch than the first liquid metal well array attached to the second interposer surface; and multiple companion component packages attached to the multiple liquid metal well arrays attached to the first interposer surface.

11 . The electronic system of claim 1 , including:
a pin grid socket attached to the first liquid metal well array on a first side of the pin grid socket and attached to a printed circuit board (PCB) on a second side of the pin grid socket; wherein a pitch of the first liquid metal well array matches a pin pitch of the pin grid socket and a pitch of the second liquid metal well array is a finer pitch than the pitch of the first liquid metal well array.

12 . The electronic system of claim 1 , including multiple pin grid sockets, each pin grid socket attached to a portion of the multiple liquid metal wells of the first liquid metal well array on a first side of the pin grid socket and attached to a printed circuit board (PCB) on a second side of the pin grid socket.

13 . A method of forming an electronic device, the method comprising:
placing a processor package on a first interposer surface of an interposer, the interposer including electrically conductive interposer interconnect and the processor package electrically connected to the interposer interconnect; attaching a first surface of a first liquid metal well array to a second interposer surface and the interposer interconnect; attaching a first array surface of a second liquid metal well array to the first interposer surface and the interposer interconnect; and attaching a companion component package to a second array surface of the second liquid metal well array, wherein the companion component package includes a companion component to a processor of the processor package.

14 . The method of claim 13 , including:
attaching the first liquid metal well array to a mother board; and wherein a pitch of the first liquid metal well array matches a pitch of the mother board interconnect and a pitch of the second liquid metal well array is a finer pitch than the pitch of the first liquid metal well array.

15 . The method of claim 13 , including:
disposing conductive pillars on the first interposer, wherein the conductive pillars are electrically connected to the interposer interconnect; and wherein attaching the first array surface of the second liquid metal array includes attaching the liquid metal wells of the second liquid metal array to the conductive pillars on the first interposer surface.

16 . The method of claim 13 , including:
disposing contact pads on the first interposer surface, wherein the contact pads are electrically connected to the interposer interconnect; and wherein attaching the first array surface of the second liquid metal array includes attaching the first array surface of the second liquid metal array to the contact pads on the first interposer surface.

17 . An electronic system, comprising:
a first interposer including electrically conductive interposer interconnect; a first processor package including at least one processor integrated circuit (IC), the processor package attached to a first surface of the first interposer and connected to the first interposer interconnect; a first liquid metal well array including multiple liquid metal wells attached to a second surface of the first interposer and connected to the first interposer interconnect; a second interposer including electrically conductive interconnect; an IC package attached to a first surface of the second interposer and connected to the second interposer interconnect; a second liquid metal well array including multiple liquid metal wells attached to a second surface of the second interposer and connected to the second interposer interconnect; and wherein the first liquid metal well array is attached to the second surface of the second interposer and connected to the second interposer interconnect, and the second liquid metal well array is attached to the second surface of the first interposer and connected to the first interposer interconnect.

18 . The electronic system of claim 17 , wherein the first and second interposers are first and second mother boards.

19 . The electronic system of claim 17 , including a companion component to the processor IC attached to the first surface of the first interposer and connected to the first interposer interconnect.

20 . The electronic system of claim 17 ,
wherein the IC package of the second interposer is a second processor package including a second processor IC; and wherein the second interposer includes a companion component to the second processor IC attached to the first surface of the second interposer and connected to the second interposer interconnect.

21 . The elec

Assignees

• Intel Corp

Inventors

• Meyyappan Karumbu
• Smalley Jeffory L
• Murtagian Gregorio
• Nekkanty Srikant
• Tadayon Pooya
• Moret Eric J M
• Sahu Bijoyraj

Classifications

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/611 Primary

  for connecting multiple chips together · CPC title

• H10W40/22

  characterised by their shape, e.g. having conical or cylindrical projections · CPC title