Electronic device having substrate

Patent metadata

Field	Value
Publication number	US-2023187361-A1
Application number	US-202117550474-A
Country	US
Kind code	A1
Filing date	Dec 14, 2021
Priority date	Dec 14, 2021
Publication date	Jun 15, 2023
Grant date	—

Abstract

An electronic device includes a substrate, an outer layer, a conductive line layer, and a switchable circuit chip. The substrate has a plurality of having a plurality of first vias. The outer layer is disposed on a side of the substrate and has a plurality of second vias. The first vias have a larger distribution density or quantity than the second vias, so that a part of the first vias are electrically connected to the second vias, and another part of the first vias are electrically floating. The conductive line layer is disposed on the outer layer and has a plurality of conductive traces. The conductive traces are electrically connected to the second vias. The switchable circuit chip is electrically connected to the first vias. The conductive traces are electrically connected to the switchable circuit chip. The switchable circuit chip is configured for controlling an electrical connecting relationship between the conductive traces and the first vias and an electrical connecting relationship among the conductive traces.

First claim

What is claimed is:

1 . An electronic device, comprising:
a substrate, having a plurality of first vias; an outer layer, having a plurality of second vias, wherein the outer layer is disposed on a side of the substrate, and the first vias have a larger distribution density or quantity than the second vias, so that a part of the first vias are electrically connected to the second vias, and another part of the first vias are electrically floating; a conductive line layer, disposed on the outer layer, wherein the conductive line layer has a plurality of conductive traces, and at least one of the conductive traces is electrically connected to at least one of the second vias; and a switchable circuit chip, electrically connected to at least one of the first vias, wherein at least one plurality of the conductive traces of the conductive line layer are electrically connected to the switchable circuit chip, and the switchable circuit chip is configured for controlling an electrical connecting relationship between at least one plurality of the conductive traces and at least one of the first vias.

2 . The electronic device according to claim 1 , wherein the switchable circuit chip is disposed on the substrate, the switchable circuit chip is disposed in the outer layer, the conductive line layer covers the switchable circuit chip and the outer layer, and the switchable circuit chip is directly electrically connected to at least one of the first vias.

3 . The electronic device according to claim 1 , wherein the switchable circuit chip is disposed on the outer layer, the conductive line layer covers the switchable circuit chip and the outer layer, and the switchable circuit chip is electrically connected to at least one of the first vias through at least one of the second vias.

4 . The electronic device according to claim 1 , wherein the substrate has a cavity, the switchable circuit chip is disposed in the cavity, the outer layer covers the switchable circuit chip and the substrate, the switchable circuit chip is directly electrically connected to at least one of the first vias, the outer layer further has a plurality of third vias, the third vias are electrically connected to the switchable circuit chip, and at least one plurality of the conductive traces of the conductive line layer are electrically connected to the switchable circuit chip through the third vias.

5 . The electronic device according to claim 1 , further comprising an operating chip, wherein the operating chip is disposed on the conductive line layer, the operating chip is electrically connected to the switchable circuit chip through at least one of the conductive traces of the conductive line layer, the switchable circuit chip comprises a switch array, the switch array provides a plurality of connecting path configurations, the operating chip comprises a memory unit and a controlling unit electrically connected to the memory unit, the memory unit stores a configuration command, and the controlling unit is configured for enabling one of the connecting path configurations according to the configuration command.

6 . The electronic device according to claim 1 , further comprising an operating chip, wherein the operating chip is electrically connected to the substrate, the operating chip is electrically connected to the switchable circuit chip through the substrate, the switchable circuit chip comprises a switch array, the switch array provides a plurality of connecting path configurations, the operating chip comprises a memory unit and a controlling unit electrically connected to the memory unit, the memory unit stores a configuration command, and the controlling unit is configured for enabling one of the connecting path configurations according to the configuration command.

7 . The electronic device according to claim 1 , further comprising an operating chip, wherein the operating chip is disposed on the conductive line layer, the operating chip is electrically connected to the switchable circuit chip through at least one of the conductive traces of the conductive line layer, the switchable circuit chip comprises a switch array and a controlling unit electrically connected to the switch array, the switch array provides a plurality of connecting path configurations, the operating chip comprises a memory unit, the memory unit stores a configuration command, and the controlling unit is configured for enabling one of the connecting path configurations according to the configuration command.

8 . The electronic device according to claim 1 , further comprising an operating chip, wherein the operating chip is electrically connected to the substrate, the operating chip is electrically connected to the switchable circuit chip through the substrate, the switchable circuit chip comprises a switch array and a controlling unit electrically connected to the switch array, the switch array provides a plurality of connecting path configurations, the operating chip comprises a memory unit, the memory unit stores a configuration command, and the controlling unit is configured for enabling one of the connecting path configurations according to the configuration command.

9 . The electronic device according to claim 1 , wherein the outer layer comprises a first dielectric contacting each of the second vias and made of a polymer or a molding compound, and the conductive line layer comprises a second dielectric contacting each of the conductive traces and made of the polymer or the molding compound.

10 . The electronic device according to claim 9 , wherein the polymer is selected from a group consisting of polybenzoxazole and polyimide.

11 . The electronic device according to claim 1 , further comprising a plurality of first external bumps and a plurality of a second external bumps, wherein the first external bumps are disposed on a surface of the substrate located away from the conductive line layer and electrically connected to the first vias, and the second external bumps are disposed on a surface of the conductive line layer located away from the substrate and electrically connected to the conductive traces.

12 . The electronic device according to claim 11 , further comprising at least one external electronic element, wherein the at least one external electronic element is disposed on the conductive line layer, the at least one external electronic element is electrically connected to at least one of the second external bumps through at least another one of the second external bumps, at least one of the conductive traces of the conductive line layer, the switchable circuit chip, and at least another one of the conductive traces.

13 . The electronic device according to claim 11 , further comprising at least one external electronic element, wherein the at least one external electronic element is disposed on the conductive line layer, the at least one external electronic element is electrically connected to at least one of the first external bumps through at least one of the second external bumps, at least one of the conductive traces of the conductive line layer, the switchable circuit chip, and at least one of the first vias.

14 . The electronic device according to claim 11 , further comprising a plurality of external electronic elements, wherein the external electronic elements are disposed on the conductive line layer, the external electronic elements are electrically connected to each other through at least one plurality of the second external bumps, at least one plurality of the conductive traces of the conductive line layer, and the switchable circuit chip.

15 . The electro

Assignees

• Ind Tech Res Inst

Inventors

• Hung Tsung-Yi
• Wu Shih-Hsien

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title