Semiconductor device

Patent metadata

Field	Value
Publication number	US-2023171950-A1
Application number	US-202217940323-A
Country	US
Kind code	A1
Filing date	Sep 8, 2022
Priority date	Nov 29, 2021
Publication date	Jun 1, 2023
Grant date	—

Abstract

A semiconductor device includes a plurality of semiconductor patterns stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of a substrate, and extending in a second direction, parallel to the upper surface of the substrate, a plurality of first conductive patterns extending in a third direction, perpendicular to the first direction and the second direction, on the plurality of semiconductor patterns, a plurality of second conductive patterns extending in the first direction on the substrate, a plurality of capacitors electrically connected to the plurality of semiconductor patterns, respectively, and at least one epitaxial layer disposed to be in contact with at least one of both end surfaces of at least one of the plurality of semiconductor patterns and including an impurity.

First claim

1 . A semiconductor device comprising:
a plurality of semiconductor patterns stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of a substrate, and extending in a second direction, parallel to the upper surface of the substrate; a plurality of first conductive patterns extending in a third direction, perpendicular to the first direction and the second direction, on the plurality of semiconductor patterns; a plurality of second conductive patterns extending in the first direction on the substrate; a plurality of capacitors, each of the plurality of capacitors electrically connected to a corresponding one of the plurality of semiconductor patterns; and at least one epitaxial layer disposed to be in contact with at least one of both end surfaces of at least one of the plurality of semiconductor patterns and including an impurity.

2 . The semiconductor device of claim 1 , wherein the at least one epitaxial layer has a facet shape grown according to a crystal orientation of a semiconductor material layer of the semiconductor pattern.

3 . The semiconductor device of claim 1 , wherein the at least one epitaxial layer has a first side surface inclined with respect to an upper surface of the semiconductor pattern and a second side surface inclined with respect to a lower surface of the semiconductor pattern.

4 . The semiconductor device of claim 3 ,
wherein an angle between the first side surface of the at least one epitaxial layer and the upper surface of the semiconductor pattern is an obtuse angle, and wherein an angle between the second side surface of the at least one epitaxial layer and the lower surface of the semiconductor pattern is an obtuse angle.

5 . The semiconductor device of claim 1 ,
wherein the plurality of first conductive patterns intersect the plurality of semiconductor patterns, respectively, and wherein the plurality of second conductive patterns are disposed to be adjacent to first end surfaces of the plurality of semiconductor patterns.

6 . The semiconductor device of claim 5 , wherein the at least one epitaxial layer includes:
a plurality of first epitaxial layers disposed between first end surfaces of the plurality of semiconductor patterns and the plurality of second conductive patterns; and a plurality of second epitaxial layers disposed between second end surfaces of the plurality of semiconductor patterns and the plurality of capacitors.

7 . The semiconductor device of claim 6 , further comprising:
a plurality of first metal-semiconductor compound layers disposed between the plurality of first epitaxial layers and the plurality of second conductive patterns, respectively; and a plurality of second metal-semiconductor compound layers disposed between the plurality of second epitaxial layers and the plurality of capacitors, respectively.

8 . The semiconductor device of claim 6 , wherein the second conductive pattern has an inclined inner side surface facing an inclined side surface of each of the plurality of first epitaxial layers.

9 . The semiconductor device of claim 5 ,
wherein each of the plurality of capacitors includes a first electrode, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, and wherein the first electrode covers the inclined side surface of a corresponding one of the plurality of second epitaxial layers, and includes a portion protruding toward the second electrode.

10 . The semiconductor device of claim 1 ,
wherein the plurality of first conductive patterns are disposed to be adjacent to first end surfaces of the plurality of semiconductor patterns, wherein the plurality of second conductive patterns intersect the plurality of semiconductor patterns, respectively, and wherein the at least one epitaxial layer includes:
a plurality of first epitaxial layers disposed between first end surfaces of the plurality of semiconductor patterns and the plurality of first conductive patterns; and
a plurality of second epitaxial layers disposed between second end surfaces of the plurality of semiconductor patterns and the plurality of capacitors.

11 . A semiconductor device comprising:
a plurality of structures and a plurality of first insulating layers alternately stacked on a substrate; and a vertical conductive pattern extending vertically in a first direction, perpendicular to an upper surface of the substrate, on the substrate, wherein each of the plurality of structures includes:
a capacitor including a capacitor electrode and a dielectric layer;
a semiconductor pattern including a first impurity region electrically connected to the vertical conductive pattern, a second impurity region electrically connected to the capacitor electrode, and a channel region between the first impurity region and the second impurity region;
a gate electrode disposed between the channel region of the semiconductor pattern and the plurality of first insulating layers and intersecting the vertical conductive pattern to extend in a second direction, parallel to the upper surface of the substrate;
at least one epitaxial layer disposed to be in contact with at least one of the first impurity region and the second impurity region of the semiconductor pattern and including an impurity having a concentration greater than both a concentration of the first impurity region and a concentration of the second impurity region;
a gate dielectric layer between the gate electrode and the semiconductor pattern;
a gate capping layer between the gate electrode and the vertical conductive pattern; and
a second insulating layer between the gate electrode and the capacitor electrode.

12 . The semiconductor device of claim 11 , wherein the at least one epitaxial layer has a cross-section having a triangle, a quadrangle, a pentagon, a hexagon, an octagon, a rhombus, a circle, or an ellipse.

13 . The semiconductor device of claim 11 , wherein each of the plurality of structures further includes at least one metal-semiconductor compound layer surrounding a surface of the at least one epitaxial layer.

14 . The semiconductor device of claim 11 , wherein a length between an upper end and a lower end of the at least one epitaxial layer is longer than a length between an upper surface and a lower surface of the semiconductor pattern in the first direction.

15 . The semiconductor device of claim 11 ,
wherein the at least one epitaxial layer includes an impurity, and wherein the impurity includes at least one of Ph, As, B, C, and Ga.

16 . The semiconductor device of claim 11 , wherein the at least one epitaxial layer extends from the first impurity region and overlaps the vertical conductive pattern in the first direction.

17 . The semiconductor device of claim 11 , wherein the at least one epitaxial layer extends from the second impurity region and overlaps the capacitor electrode in the first direction.

18 . The semiconductor device of claim 11 , wherein the first insulating layer extends to be longer than the second insulating layer horizontally.

19 . A semiconductor device comprising:
a plurality of semiconductor patterns extending in a first direction parallel to an upper surface of a substrate and stacked to be spaced apart from each other on the substrate; a conductive pattern intersecting the plurality of semiconductor patterns and extending in a second direction, perpendicular to the first direction; a capacitor electrically connected to the semiconductor pattern; an epitaxial layer extendin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jang Sunguk
• Lee Kongsoo
• Hong Sahwan

Classifications

• H10D1/711

  having non-planar surfaces, e.g. formed by texturisation · CPC title

• H10D1/714 Primary

  having horizontal extensions · CPC title

• H10B12/315 Primary

  with the capacitor higher than a bit line · CPC title

• H01L27/10814 Primary

  Electricity · mapped topic

• H10B12/318 Primary

  the storage electrode having multiple segments · CPC title